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Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesqu 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0999075 (1997-12-29)
발명자 / 주소
  • Chen Chao-Cheng,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd., TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 61  인용 특허 : 15

초록

A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a low dielectric constant dielectric layer, where the low dielectric constant diele

대표청구항

[ What is claimed is:] [1.] A method for forming a via through a dielectric layer within a microelectronics fabrication comprising:providing a substrate employed within a microelectronics fabrication;forming over the substrate a dielectric layer, the dielectric layer being formed from a silsesquioxa

이 특허에 인용된 특허 (15)

  1. Shinagawa Keisuke (Kawasaki JPX) Fujimura Shuzo (Tokyo JPX) Hikazutani Kenichi (Kuwana JPX), Ashing method for removing an organic film on a substance of a semiconductor device under fabrication.
  2. Kadomura Shingo (Kanagawa JPX), Dry etching method.
  3. Araki Yoichi,JPX ; Inazawa Koichiro,JPX ; Furuya Sachiko,JPX ; Ogasawara Masahiro,JPX ; Koshimizu Chishio,JPX ; Song Tiejun,JPX, Etching process.
  4. Ishida Tomoaki (Hyogo JPX) Kawai Kenji (Hyogo JPX) Akazawa Moriaki (Hyogo JPX) Maruyama Takahiro (Hyogo JPX) Ogawa Toshiaki (Hyogo JPX), Method for cleaning semiconductor devices.
  5. Chao L. C.,TWX ; Huang M. H.,TWX ; Yu C. H.,TWX, Method for etching metal lines with enhanced profile control.
  6. Wu Jiunn Y. (Dou-Lio TWX) Lur Water (Taipei TWX), Method for metal deposition without poison via.
  7. Kuo So Wen (Hsin-chu TWX) Tsai Chia-Shiung (Hsin-chu TWX), Method for reducing contact resistance.
  8. Yeh Rann Shyan,TWX ; Chang Chao-Hsin,TWX ; Chang Hsien-Wen,TWX, Method for reducing precipitate defects using a plasma treatment post BPSG etchback.
  9. Chien Rong-Wu,TWX ; Lee Hsiu-Lan,TWX ; Yen Tzu-Shih,TWX, Method for removing fluorinated photoresist layers from semiconductor substrates.
  10. Lo Yung Tsun,TWX ; Yi Guan Jiun,TWX ; Lin Chi Hen,TWX ; Jih Jyh Ming,TWX, Method of preventing defects and particles produced after tungsten etch back.
  11. Jones Curtis S. (Boise ID) Crane William J. (Boise ID) Gilchrist Robin L. (Boise ID) Langley Rod C. (Boise ID), Method to remove fluorine residues from bond pads.
  12. Mihara Satoru (Kawasaki JPX) Komada Daisuke (Kasugai JPX), Plasma ashing method with oxygen pretreatment.
  13. Mak Steven (Pleasanton CA) Shieh Brian (Fremont CA) Rhoades Charles S. (Los Gatos CA), Plasma etching using xenon.
  14. Bersin Richard L. ; Xu Han, Processes for cleaning and stripping photoresist from surfaces of semiconductor wafers.
  15. Jolly Gurvinder (Orleans CAX) Yung Bud K. (Ottawa CAX), Tapering sidewalls of via holes.

이 특허를 인용한 특허 (61)

  1. Shields Jeffrey A., Borderless vias without degradation of HSQ gap fill layers.
  2. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  3. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  4. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.
  5. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.
  6. Jang, Syun-Ming, Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material.
  7. Zhu, Helen; Annapragada, Rao, Etch back process using nitrous oxide.
  8. Watanabe, Hikaru; Tsuji, Akihiro, Etching method.
  9. Q. Z. Liu ; Bin Zhao, Fabrication of improved low-k dielectric structures.
  10. Goto, Haruhiro Harry; Harshbarger, William R.; Shang, Quanyuan; Law, Kam S., Fluorine process for cleaning semiconductor process chamber.
  11. James Harold Powers ; Carl Edmond Sullivan, Ink jet printheads and methods therefor.
  12. Yau, Wai-Fan; Cheung, David; Jeng, Shin-Puu; Liu, Kuowei; Yu, Yung-Cheng, Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond.
  13. Mark Haley ; Delbert Parks ; Judy Galloway, Method for cleaning integrated circuit bonding pads.
  14. Tamaoka Eiji,JPX ; Aoi Nobuo,JPX ; Ueda Tetsuya,JPX, Method for fabricating semiconductor device.
  15. Tanaka Tsuyoshi,JPX ; Nishioka Yasushiro,JPX, Method for forming a semiconductor multilayer interconnect device using SOG and polyimide.
  16. Ho Yueh-Feng,TWX, Method for forming via hole.
  17. Patil, Girish Shivaji; Vaideeswaran, Karthik, Method for making a micro-fluid ejection device.
  18. Sakata, Toyokazu, Method of fabricating a semiconductor device.
  19. Ryuichi Kanamura JP, Method of manufacturing a semiconductor device.
  20. Teng-Chun Tsai TW; Hsueh-Chung Chen TW; Ming-Sheng Yang TW, Method of manufacturing dual damascene structure.
  21. Park Jae-Hyun,KRX ; Yoon Han-Sik,KRX, Method of preventing bowing in a via formation process.
  22. Chen, Shyng-Tsong; Klymko, Nancy R.; Madan, Anita; Mehta, Sanjay; Molis, Steven E., Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species.
  23. Panda, Siddhartha; Ranade, Rajiv M.; Mathad, Gangadhara S., Method to increase the etch rate and depth in high aspect ratio structure.
  24. Fu,Wen Jui; Shen,Shang Ru; Shen,Yun Hung; Chen,Chao Cheng, Method to reduce the fluorine contamination on the Al/Al-Cu pad by a post high cathod temperature plasma treatment.
  25. Li, Li, Methods for fabricating residue-free contact openings.
  26. Li, Li, Methods for fabricating residue-free contact openings.
  27. Li,Li, Methods for fabricating residue-free contact openings.
  28. Annapragada Rao V., Methods for making reliable via structures having hydrophobic inner wall surfaces.
  29. Ban, Keun Do; Bok, Cheol Kyu; Yoo, Min Ae; Park, Jong Cheon, Methods of fabricating interconnection structures.
  30. Ban, Keun Do; Bok, Cheol Kyu; Yoo, Min Ae; Park, Jong Cheon, Methods of fabricating interconnection structures.
  31. Zhu,Helen; Annapragada,Rao, Nitrous oxide stripping process for organosilicate glass.
  32. Shang, Quanyuan; Yadav, Sanjay; Harshbarger, William R.; Law, Kam S., On-site cleaning gas generation for process chamber cleaning.
  33. Shang,Quanyuan; Yadav,Sanjay; Harshbarger,William R.; Law,Kam S., On-site cleaning gas generation for process chamber cleaning.
  34. Dunne Jude ; Kennedy Joseph ; Luo Leroy Laizhong ; Howell Diane Cecile ; Kuhl Nicole Eliette Charlotte, Photoresist ashing process for organic and inorganic polymer dielectric materials.
  35. Mohammad R. Rakhshandehroo ; Mark S. Chang ; Angela T. Hui, Plasma treatment for polymer removal after via etch.
  36. Ang Arthur,SGX ; Yi Xu,SGX, Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening.
  37. Annapragada, Rao V.; Morey, Ian J.; Ho, Chok W., Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications.
  38. Kirkpatrick, Brian K.; Morrison, Michael; McKerrow, Andrew J.; Newton, Kenneth J.; Anderson, Dirk N., Pre-pattern surface modification of low-k dielectrics.
  39. Cote, William J.; Dalton, Timothy J.; Dev, Prakash Chimanlal; Edelstein, Daniel C.; Halle, Scott D.; Lee, Gill Yong; Mahorowala, Arpan P., Process for forming a damascene structure.
  40. Usami Tatsuya,JPX ; Ohto Kouichi,JPX ; Ueda Yasuhiko,JPX, Process of fabricating semiconductor device having ashing step for photo-resist mask in plasma produced from N.sub.x H.sub.y gas.
  41. Diao, Jie; Leung, Garlen C.; Lee, Christopher Heung-Gyun; Karuppiah, Lakshmanan, Process sequence to achieve global planarity using a combination of fixed abrasive and high selectivity slurry for pre-metal dielectric CMP applications.
  42. Chang Chung-Long,TWX ; Jang Syun-Ming,TWX, Process to improve adhesion of HSQ to underlying materials.
  43. Li, Li, Residue-free contact openings and methods for fabricating same.
  44. Dunham,Timothy G.; Hall,Ezra D. B.; Landis,Howard S.; Lavin,Mark A.; Leipold,William C., Shapes-based migration of aluminum designs to copper damascence.
  45. Dunham, Timothy G.; Hall, Ezra D. B.; Landis, Howard S.; Lavin, Mark A.; Leipold, William C., Shapes-based migration of aluminum designs to copper damascene.
  46. Dunham, Timothy G.; Hall, Ezra D. B.; Landis, Howard S.; Lavin, Mark A.; Leipold, William C., Shapes-based migration of aluminum designs to copper damascene.
  47. Dunham,Timothy G.; Hall,Ezra D. B.; Landis,Howard S.; Lavin,Mark A.; Leipold,William C., Shapes-based migration of aluminum designs to copper damascene.
  48. Dunham,Timothy G.; Hall,Ezra D. B.; Landis,Howard S.; Lavin,Mark A.; Leipold,William C., Shapes-based migration of aluminum designs to copper damascene.
  49. Chen, Shyng-Tsong; Lin, Qinghuang; Malone, Kelly; Mehta, Sanjay; Spooner, Terry A.; Yang, Chih-Chao, Surface treatment of inter-layer dielectric.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. I. T. Chen TW; Horng-Bor Lu TW, Treatment on silicon oxynitride.
  58. Zhu, Helen H.; Bowers, James R.; Morey, Ian J.; Babie, Wayne; Goss, Michael, Unique process chemistry for etching organic low-k materials.
  59. Ho, Chok W.; Tang, Kuo-Lung; Lee, Chung-Ju, Use of ammonia for etching organic low-k dielectrics.
  60. Ho,Chok W.; Tang,Kuo Lung; Lee,Chung Ju, Use of ammonia for etching organic low-k dielectrics.
  61. Ho, Chok W., Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics.
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