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Method for fabricating a semiconductor device having a nitrogen diffusion layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/336
  • H01L-021/223
  • H01L-021/331
  • H01L-021/265
출원번호 US-0796710 (1997-02-06)
우선권정보 JP-0326507 (1996-12-06)
발명자 / 주소
  • Arai Masatoshi,JPX
  • Segawa Mizuki,JPX
  • Yabu Toshiki,JPX
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd., JPX
대리인 / 주소
    McDermott, Will & Emery
인용정보 피인용 횟수 : 73  인용 특허 : 11

초록

An element isolator is formed in a silicon substrate. A gate oxide film and a gate electrode are formed overlying the silicon substrate. Subsequently, a four-step large-tilted-angle ion implant is performed in which ions of nitrogen are implanted at an angle of tilt of 25 degrees, to form an oxynitr

대표청구항

[ The invention claimed is:] [1.] A method of fabricating a semiconductor device having a MIS-type field effect transistor, said semiconductor device fabrication method comprising the steps of:(a) a first step of forming on a semiconductor substrate an element isolator which encloses an active regio

이 특허에 인용된 특허 (11)

  1. Kusunoki Shigeru (Hyogo JPX) Inuishi Masahide (Hyogo JPX), Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing me.
  2. Gardner Mark I. ; Fulford ; Jr. H. Jim, High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel.
  3. Hao Ming-yin ; Rakkhit Rajat, Hot-carrier reliability in submicron MOS devices by oxynitridation.
  4. Anand, Kranti; Strain, Robert J., Ion implantation to increase emitter energy gap in bipolar transistors.
  5. Loh Ying-Tsong (Saratoga CA) Ding Lily (Fremont CA) Nowak Edward D. (Pleasanton CA), Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor.
  6. Lee Sang Don,KRX, Method for manufacturing semiconductor device.
  7. Pan Yang,SGX, Method for minimizing the hot carrier effect in N-MOSFET devices.
  8. Ahmad Aftab (Boise ID) Thakur Randhir P. S. (Boise ID), Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron inject.
  9. Price J. B. (Scottsdale AZ) Reed Edwin E. (Pflugerville TX) Rutledge James L. (Tempe AZ), Plasma enhanced thermal treatment apparatus.
  10. Oda Hidekazu (Hyogo JPX) Ueno Shuichi (Hyogo JPX) Yamaguchi Takehisa (Hyogo JPX), Semiconductor MOSFET device having a shallow nitrogen implanted channel region.
  11. Kawasaki Youji (Hyogo JPX) Takahashi Taketo (Hyogo JPX) Murakami Takashi (Hyogo JPX), Semiconductor device having MOS transistor.

이 특허를 인용한 특허 (73)

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  7. Cui, Hao; Burke, Peter A.; Catabay, Wilbur G., Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures.
  8. Ki Jae Huh KR; Duk Hee Lee KR, Fabrication method of semiconductor device.
  9. Ahmad,Aftab, Fabrication of integrated devices using nitrogen implantation.
  10. Wang Janet, Flash EPROM cell with reduced short channel effect and method for providing same.
  11. Baldwin, Gregory Charles; Blatchford, James Walter, Flexible integration of logic blocks with transistors of different threshold voltages.
  12. Chakravarthi, Srinivasan; Chidambaram, Pr; Bowen, Robert C.; Bu, Haowen, Forming a retrograde well in a transistor to enhance performance of the transistor.
  13. Chakravarthi,Srinivasan; Chidambaram,Pr; Bowen,Robert C.; Bu,Haowen, Forming a retrograde well in a transistor to enhance performance of the transistor.
  14. Trivedi Jigish D. ; Wang Zhongze ; Yang Rongsheng, Integrated circuitry and semiconductor processing method of forming field effect transistors.
  15. Trivedi, Jigish D.; Wang, Zhongze; Yang, Rongsheng, MOS transistors with nitrogen in the gate oxide of the p-channel transistor.
  16. Mouli, Chandra V.; Roberts, Ceredig, Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxide MOSFETs.
  17. Mouli,Chandra V.; Roberts,Ceredig, Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs.
  18. Enicks,Darwin Gene, Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement.
  19. Chiang,Mu Chi; Lin,Hsien Chin; Shih,Jiaw Ren, Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a Teos liner deposition.
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  21. Liaw, Jhon Jhy; Hsieh, Chih-Hung, Method for manufacturing SRAM devices with reduced threshold voltage deviation.
  22. Dirk Schumann DE, Method for manufacturing an integrated circuit with low threshold voltage differences of the transistors therein.
  23. Shin, Jung-Wook; Kim, Jae-Seung; Kim, Hong-Seub, Method for manufacturing low voltage flash memory.
  24. Nagayama Tetsuji,JPX, Method for producing semiconductor device.
  25. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.
  26. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.
  27. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.
  28. Irino, Kiyoshi, Method of fabricating a semiconductor device containing nitrogen in a gate oxide film.
  29. Irino,Kiyoshi, Method of fabricating a semiconductor device containing nitrogen in an oxide film.
  30. Beyer, Klaus D.; Jamin, Fen F.; Varekamp, Patrick R., Method of formation of an oxynitride shallow trench isolation.
  31. Moore, John T.; DeBoer, Scott J., Method of forming a capacitor dielectric layer.
  32. Sandhu, Gurtej S.; Moore, John T.; Rueger, Neal R., Method of forming a nitrogen-enriched region within silicon-oxide-containing masses.
  33. Beaman, Kevin L.; Moore, John T., Method of forming a structure over a semiconductor substrate.
  34. Beaman, Kevin L.; Moore, John T., Method of forming a structure over a semiconductor substrate.
  35. Beaman,Kevin L.; Moore,John T., Method of forming a structure over a semiconductor substrate.
  36. Tran, Luan C., Method of forming memory cells and a method of isolating a single row of memory cells.
  37. Tran, Luan C., Method of forming memory cells in an array.
  38. Tran,Luan C., Method of forming memory cells in an array.
  39. Moore, John T., Method of forming transistors associated with semiconductor substrates comprising forming a nitrogen-comprising region across an oxide region of a transistor gate.
  40. Gardner Mark I. ; Fulford H. Jim, Method of making high performance transistors using channel modulated implant for ultra thin oxide formation.
  41. Wu, Zhiqiang; Sheu, Yi-Ming; Yu, Tsung-Hsing; Cheng, Kuan-Lun; Tsao, Chih-Pin; Chen, Wen-Yuan; Cheng, Chun-Fu; Wang, Chih-Ching, Method of manufacturing an integrated circuit.
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  48. Moore, John T., Methods of forming oxide regions over semiconductor substrates.
  49. Moore, John T., Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices.
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  57. Klaus D. Beyer ; Fen F. Jamin ; Patrick R. Varekamp, Oxynitride shallow trench isolation and method of formation.
  58. Jigish D. Trivedi ; Zhongze Wang ; Rongsheng Yang, P-type FET in a CMOS with nitrogen atoms in the gate dielectric.
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  68. Trivedi, Jigish D.; Wang, Zhongze; Yang, Rongsheng, Semiconductor processing method of forming field effect transistors.
  69. Chan,Victor W. C.; Lee,Yong M.; Yang,Haining, Structure and method of applying stresses to PFET and NFET transistor channels for improved performance.
  70. Pei, Chengwen; Booth, Jr., Roger A.; Cheng, Kangguo; Ervin, Joseph; Todi, Ravi M.; Wang, Geng, Structure and method to fabricate pFETS with superior GIDL by localizing workfunction.
  71. Moore, John T., Transistor devices.
  72. Sandhu,Gurtej S.; Moore,John T.; Rueger,Neal R., Transistor structures.
  73. Sandhu, Gurtej S.; Moore, John T.; Rueger, Neal R., Transistor structures, methods of incorporating nitrogen into silicon-oxide-containing layers; and methods of forming transistors.
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