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Process for forming a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/285
출원번호 US-0963436 (1997-11-03)
발명자 / 주소
  • Tobin Philip J.
  • Hegde Rama I.
  • Tseng Hsing-Huang
  • O'Meara David
  • Wang Victor
출원인 / 주소
  • Motorola, Inc.
인용정보 피인용 횟수 : 116  인용 특허 : 19

초록

A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface layer (202). Bul

대표청구항

[ What is claimed is:] [1.] A method for forming a semiconductor device, the method comprising:placing a semiconductor substrate into a first chamber;forming a dielectric overlying a semiconductor substrate, the dielectric includes a first layer formed within the first chamber, wherein:during the fo

이 특허에 인용된 특허 (19)

  1. Kawamura Takao (17-11 ; Takakura-dai 1-chome Sakai-shi ; Osaka JPX) Iwano Hideaki (Kagoshima JPX) Miyamoto Naooki (Kagoshima JPX) Nishiguchi Yasuo (Kagoshima JPX), Electrophotographic sensitive member with amorphous Si barrier layer.
  2. Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
  3. Aoki ; Teruaki ; Abe ; Motoaki, Method for manufacture of a semiconductor device.
  4. Schmitt ; III Jerome J. (New Haven CT) Halpern Bret L. (Bethany CT), Microwave plasma assisted supersonic gas jet deposition of thin film materials.
  5. Kauffman Ralph ; Lee Roger, Nonvolatile floating gate memory with improved interploy dielectric.
  6. Kim Young O. (Marlboro NJ) Manchanda Lalita (Aberdeen NJ) Weber Gary R. (Whitehouse Station NJ), Oxynitride-dioxide composite gate dielectric process for MOS manufacture.
  7. Woo Been-Jon K. (20675 Woodward Ct. Saratoga CA 95070) Atwood Gregory (2495 Marsha Way San Jose CA 95132) Lai Stefan K. C. (2613 Lincoln Ave. Belmont CA 94002) Ong T. C. (1820 Mayall Ct. San Jose CA , Process for fabricating a flash EPROM having reduced cell size.
  8. Okada Yoshio (Austin TX) Tobin Philip J. (Austin TX), Process for fabricating a semiconductor device having a high reliability dielectric material.
  9. Zhang Hongyong (Kanagawa JPX) Ohnuma Hideto (Kanagawa JPX) Takemura Yasuhiko (Kanagawa JPX), Process for fabricating thin film transistor.
  10. Ito Takashi (Kawasaki JPX) Nozaki Takao (Yokohama JPX), Process for producing a semiconductor device having a silicon oxynitride insulative film.
  11. Sung Janmye,TWX, Reduced mask DRAM process.
  12. Chapple-Sokol Jonathan D. (Poughkeepsie NY) Conti Richard A. (Mount Kisco NY) Kotecki David E. (Hopewell Junction NY) Simon Andrew H. (Fishkill NY) Tejwani Manu (Yorktown Heights NY), Safe method for etching silicon dioxide.
  13. Matsushita Takeshi (Sagamihara JPX) Hayashi Hisao (Atsugi JPX) Aoki Teruaki (Tokyo JPX) Yamoto Hisayoshi (Hatano JPX) Kawana Yoshiyuki (Atsugi JPX), Semiconductor device having oxygen doped polycrystalline passivation layer.
  14. Saitoh Manzoh (Tokyo JPX) Okamura Kenji (Tokyo JPX), Semiconductor device having polycrystalline silicon resistor.
  15. Yamazaki Kouji (Tokyo JPX) Gomi Hideki (Tokyo JPX), Semiconductor device having silicon oxynitride film with improved moisture resistance.
  16. Sakamoto Mitsuru (Tokyo JPX), Semiconductor integrated circuit device having improved trench isolation.
  17. Ping Er-Xang (Boise ID) Thakur Randhir P. S. (Boise ID), Semiconductor processing method of making a hemispherical grain (HSG) polysilicon layer.
  18. Kaganowicz Grzegorz (Belle Mead NJ) Enstrom Ronald E. (Skillman NJ) Robinson John W. (Levittown PA), Silicon oxynitride passivated semiconductor body and method of making same.
  19. Kaya Cetin (Dallas TX) Tigelaar Howard L. (Allen TX), Split metal plate capacitor and method for making the same.

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