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IC package having a single wiring sheet with a lead pattern disposed thereon 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
출원번호 US-0848585 (1997-04-29)
우선권정보 JP-0109767 (1996-04-30)
발명자 / 주소
  • Suzuki Etsuji,JPX
  • Yonezawa Akira,JPX
  • Yamazaki Hidehisa,JPX
  • Odaira Hiroshi,JPX
출원인 / 주소
  • Yamaichi Electronics Co., Ltd., JPX
대리인 / 주소
    Wenderoth, Lind & Ponack, L.L.P.
인용정보 피인용 횟수 : 71  인용 특허 : 8

초록

An IC package is provided that has a flexible wiring sheet, including an upper portion, a lower portion and a side portion which is wound around a base member over an upper surface, side surfaces and a lower surface of the base member. An IC is loaded on an upper surface of the upper flexible wiring

대표청구항

[ What is claimed is:] [1.] An integrated circuit package comprising:a base member having an upper surface, outer side surfaces, and a lower surface;a unitary wiring sheet having an upper surface, a pair of side surfaces, a pair of lower surfaces, and a pair of ends, wherein said wiring sheet is wra

이 특허에 인용된 특허 (8)

  1. Yoshii Masayuki (Osaka JPX) Mizumo Yoshiyuki (Osaka JPX) Oku Shunji (Osaka JPX) Kowa Mika (Osaka JPX), Chip mounting substrate having an integral molded projection and conductive pattern.
  2. Bates David A. (Fayetteville NY) Browne Ronald B. (Liverpool NY) Smith David P. (Clay NY), Conductively enclosed hybrid integrated circuit assembly using a silicon substrate.
  3. Yasuho Takeo (Neyagawa JPX) Matunaga Hayami (Hirakata JPX) Iwata Masao (Hirakata JPX) Furukawa Hitonobu (Neyagawa JPX), Integrated circuit device and its manufacturing method.
  4. McMahon John F. (Phoenix AZ), Method of making an electronic assembly having a flexible circuit wrapped around a substrate.
  5. Sechi Franco N. (Lawrenceville NJ), Microwave power circuit with an active device mounted on a heat dissipating substrate.
  6. Chao Chien-Chi (Taipei TWX) Lin Ming-Hane (Chu-Pei TWX) Ho Ted C. (Hsinchu TWX), Packaging assembly with consolidated common voltage connections for integrated circuits.
  7. Verspeek Johannes M. C. (Nijmegen) Laarhoven Henricus A. L. (Nijmegen) Van De Water Peter W. M. (Nijmegen) Van Middendorp Jan (Nijmegen) Boer Kornelis (Nijmegen NLX), Semiconductor device having a clamping support.
  8. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Thermally enhanced semiconductor device having exposed backside and method for making the same.

이 특허를 인용한 특허 (71)

  1. Goodwin,Paul; Wehrly, Jr.,James Douglas, Active cooling methods and apparatus for modules.
  2. Goodwin,Paul, Buffered thin module system and method.
  3. Roeters,Glen E; Ross,Andrew C, CSP chip stack with flex circuit.
  4. Taisuke Ahiko JP; Takaya Ishigaki JP; Hiroki Sato JP; Kamiya Takashi JP; Masanori Yamamoto JP, Chip-type electronic component having external electrodes that are spaced at predetermined distances from side surfaces of a ceramic substrate.
  5. Szewerenko, Leland; Partridge, Julian; Orris, Ron, Circuit module having force resistant construction.
  6. Szewerenko,Leland; Partridge,Julian; Orris,Ron, Circuit module having force resistant construction.
  7. Szewerenko, Leland; Partridge, Julian; Lieberman, Wayne; Goodwin, Paul, Circuit module turbulence enhancement systems and methods.
  8. Wehrly, Jr.,James Douglas; Wilder,James; Wolfe,Mark; Goodwin,Paul, Circuit module with thermal casing systems.
  9. Cady, James W.; Wehrly, Jr., James Douglas; Goodwin, Paul, Compact module system and method.
  10. Wehrly, Jr.,James Douglas, Composite core circuit module system and method.
  11. Asahi,Toshiyuki; Karashima,Seiji; Ichiryu,Takashi; Nakatani,Seiichi; Nishiyama,Tousaku; Hirano,Koichi; Shibata,Osamu; Nakayama,Takeshi; Saito,Yoshiyuki, Connection member and mount assembly and production method of the same.
  12. Cady, James W.; Goodwin, Paul, Die module system.
  13. Cady,James W.; Goodwin,Paul, Die module system.
  14. Thomas, John; Rapport, Russell; Washburn, Robert, Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area.
  15. Wehrly, Jr., James Douglas; Goodwin, Paul; Rapport, Russell, Flex circuit constructions for high capacity circuit module systems and methods.
  16. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Flex-based circuit module.
  17. Wehrly, Jr., James Douglas; Wilder, James; Goodwin, Paul; Wolfe, Mark, Heat sink for a high capacity thin module system.
  18. Wehrly, Jr.,James Douglas; Wilder,James; Goodwin,Paul; Wolfe,Mark, High capacity thin module system.
  19. Wehrly, Jr.,James Douglas; Wilder,James; Goodwin,Paul; Wolfe,Mark, High capacity thin module system.
  20. Goodwin, Paul, High capacity thin module system and method.
  21. Goodwin, Paul, High capacity thin module system and method.
  22. Goodwin,Paul, High capacity thin module system and method.
  23. Cady, James W.; Wilder, James; Roper, David L.; Rapport, Russell; Wehrly, Jr., James Douglas; Buchle, Jeffrey Alan, Integrated circuit stacking system.
  24. Cady, James W.; Wilder, James; Roper, David L.; Rapport, Russell; Wehrly, Jr., James Douglas; Buchle, Jeffrey Alan, Integrated circuit stacking system.
  25. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Integrated circuit stacking system and method.
  26. Cady,James W.; Wilder,James; Roper,David L.; Rapport,Russell; Wehrly, Jr.,James Douglas; Buchle,Jeffrey Alan, Integrated circuit stacking system and method.
  27. Goodwin,Paul, Inverted CSP stacking system and method.
  28. Cady,James W.; Partridge,Julian; Wehrly, Jr.,James Douglas; Wilder,James; Roper,David L.; Buchle,Jeff, Low profile chip scale stacking system and method.
  29. Cady,James W.; Partridge,Julian; Wehrly, Jr.,James Douglas; Wilder,James; Roper,David L.; Buchle,Jeff, Low profile chip scale stacking system and method.
  30. Partridge, Julian; Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Low profile stacking system and method.
  31. Partridge,Julian; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas, Low profile stacking system and method.
  32. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  33. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  34. Wehrly, Jr., James Douglas, Memory card and method for devising.
  35. Wehrly, Jr., James Douglas, Memory card and method for devising.
  36. Rapport,Russell; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas; Buchle,Jeff, Memory expansion and chip scale stacking system and method.
  37. Rapport, Russell; Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas; Buchle, Jeff, Memory expansion and integrated circuit stacking system and method.
  38. Goodwin, Paul, Memory module system and method.
  39. Asahi, Toshiyuki; Karashima, Seiji; Ichiryu, Takashi; Nakatani, Seiichi; Nishiyama, Tousaku; Hirano, Koichi; Shibata, Osamu; Nakayama, Takeshi; Saito, Yoshiyuki, Method for producing connection member.
  40. Partridge, Julian; Roper, David; Goodwin, Paul, Modified core for circuit module system and method.
  41. Roper,David L.; Hart,Curtis; Wilder,James; Bradley,Phill; Cady,James G.; Buchle,Jeff; Wehrly, Jr.,James Douglas, Modularized die stacking system and method.
  42. Goodwin, Paul; Cady, James W., Module thermal management system and method.
  43. Asahi, Toshiyuki; Karashima, Seiji; Ichiryu, Takashi; Nakatani, Seiichi; Nishiyama, Tousaku, Module with a built-in component, and electronic device with the same.
  44. Ootani Mitsuaki,JPX, Multilayered electronic part and electronic circuit module including therein the multilayered electronic part.
  45. Wehrly, Jr., James Douglas; Wolfe, Mark; Goodwin, Paul, Optimized mounting area circuit module system and method.
  46. Roper,David L.; Cady,James W.; Wilder,James; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Pitch change and chip scale stacking system.
  47. Roper,David L.; Cady,James W.; Wilder,James; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Pitch change and chip scale stacking system and method.
  48. Kiyoharu Kusano JP; Kyoko Miyazima JP, Printed circuit board for semiconductor package and method of making same.
  49. Akihiro Murata JP, Semiconductor apparatus substrate, semiconductor apparatus, and method of manufacturing thereof and electronic apparatus.
  50. Takao Matsuura JP; Yoshihiko Yamaguchi JP; Shouichi Kobayashi JP; Kouji Tsuchiya JP, Semiconductor device an a method of manufacturing the same.
  51. Matsuura, Takao; Yamaguchi, Yoshihiko; Kobayashi, Shouichi; Tsuchiya, Kouji, Semiconductor device and a method of manufacturing the same.
  52. Matsuura, Takao; Yamaguchi, Yoshihiko; Kobayashi, Shouichi; Tsuchiya, Kouji, Semiconductor device and a method of manufacturing the same.
  53. Matsuura, Takao; Yamaguchi, Yoshihiko; Kobayashi, Shouichi; Tsuchiya, Kouji, Semiconductor device and a method of manufacturing the same.
  54. Roper, David L.; Wehrly, Jr., Douglas; Wolfe, Mark, Split core circuit module.
  55. Forthun, John A., Stackable chip package with flex carrier.
  56. Isaak,Harlan R., Stackable flex circuit IC package and method of making same.
  57. Szewerenko,Leland; Goodwin,Paul; Wehrly, Jr.,James Douglas, Stackable micropackages and stacked modules.
  58. Wehrly, Jr.,James Douglas, Stacked integrated circuit module.
  59. Partridge, Julian; Wehrly, Jr., James Douglas; Roper, David L.; Villani, Joseph, Stacked module systems.
  60. Partridge,Julian; Wehrly, Jr.,James Douglas; Roper,David, Stacked module systems and method.
  61. Partridge,Julian; Wehrly, Jr.,James Douglas; Roper,David, Stacked module systems and method.
  62. Partridge, Julian; Wehrly, Jr., James Douglas, Stacked module systems and methods.
  63. Partridge,Julian; Wehrly, Jr.,James Douglas, Stacked module systems and methods.
  64. Wehrly, Jr.,James Douglas, Stacked module systems and methods.
  65. Wehrly, Jr., James Douglas, Stacked modules and method.
  66. Rapport,Russell; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Stacking system and method.
  67. Roeters,Glen E; Ross,Andrew C, Stacking system and method.
  68. Sustek, Laurent; Di Vito, Stephane, Surface mounting chip carrier module.
  69. Goodwin, Paul; Cady, James W.; Wehrly, Douglas, Thin module system and method.
  70. Goodwin,Paul, Thin module system and method.
  71. Goodwin,Paul, Thin module system and method.
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