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Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0437065 (1995-05-09)
발명자 / 주소
  • Fakhruddin Saifuddin T.
  • Sun Jiming
  • Foster Mark J.
  • Hovey Scott A.
  • Walker James L.
  • Mart Gregory Allen
  • Vanderheyden Randy J.
  • Ruthenbeck Mark A.
출원인 / 주소
  • Vantus Technology
대리인 / 주소
    Smith
인용정보 피인용 횟수 : 4  인용 특허 : 52

초록

A computer system has a processing unit with suspend/resume capability, a memory, and a hard disk drive. In response to a first command from the processor, the hard disk drive sends its status to the processor and the processor stores it in the memory. In response to a second command from the proces

대표청구항

[ The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:] [1.] An apparatus comprising: a processor which executes an application program; storage means for storing data; a peripheral having a control circuit which has an operational status, s

이 특허에 인용된 특허 (52)

  1. Arroyo Ronald X. (Elgin TX) Day Michael N. (Austin TX) Edrington Jimmie D. (Georgetown TX) Hanna James T. (Austin TX) Hunt Gary T. (Austin TX) Pancoast Steven T. (Austin TX), Apparatus and method for suspending and resuming software applications on a computer.
  2. Carter Robert R. (Cypress TX) Garner Paul M. (The Woodlands TX) Cepulis Darren J. (Houston TX) Boone Carrie (Houston TX), Apparatus for reducing computer system power consumption.
  3. Canova ; Jr. Francis J. (Boynton Beach FL) Katz Neil A. (Parkland FL) Pollitt Richard F. (Jensen Beach FL) Suarez Leopoldo L. (Boca Raton FL) Astarabadi Shaun (Irvine CA) Frank C. William (Irvine CA), Battery operated computer power management system.
  4. Pusic Vladi (San Jose CA) George Benjamin T. (Sunnyvale CA) Smith Monte E. (St. Paul MN) Johnson Craig B. (Shoreview MN), Cache/disk file status indicator with data protection feature.
  5. Tamaki Kazuyoshi (Nagoya JPX), Circuit arrangement for preventing a microcomputer from malfunctioning.
  6. Lies Kenneth A. (Lubbock TX), Clocked logic low power standby mode.
  7. Marrington S. Paul (Fyshwick CA AUX) Kiankhooy-Fard Paul (San Diego CA) Zecos P. (Del Mar CA) Rudaw Geoffrey (Nancet NY), Computer power system.
  8. Marrington S. Paul (P.O. Box 34 Fyshwick CA AUX 2609) Kiankhooy-Fard Paul (1165 Archer St. San Diego CA 92109) Zecos Paul (13367 Caminito Mar Villa Del Mar CA) Rudaw Geoffrey (43 Argow Pl. Nanuet NY , Computer power system.
  9. Nagasawa Kunihiko (Tokyo JPX), Computer system with a back-up power supply.
  10. Satoh Masaharu (Nara JPX) Hashimoto Sadakatsu (Nara JPX), Control system for multi-processor.
  11. Hillion Herv (Eindhoven NLX), Data processing apparatus with energy saving clocking device.
  12. McAnlis James C. (Bangor GB5) Kumar Kuldip (Gateshead PA GB2) Gould Robert T. M. (Downington PA), Data processor system including data-save controller for protection against loss of volatile memory information during p.
  13. Bush Kenneth L. (Cypress TX) Perry Ralph S. (Houston TX), Disk drive activity indicator.
  14. Morehouse James H. (Jamestown CO) Andrews ; Jr. Thomas L. (Boulder CO) Blagaila John H. (Boulder CO) Furay David M. (Boulder CO) Johnson Terry G. (Longmont CO), Disk drive apparatus using dynamic loading/unloading.
  15. Saitou Yosio (Oome JPX), Display panel open/closed detection mechanism, and portable electronic apparatus using the same.
  16. Swartz Jack S. (San Jose CA), Dual mode actuator for disk drive useful with a portable computer.
  17. Garner Paul M. (The Woodlands TX) Boone Carrie (Houston TX) Cepulis Darren J. (Houston TX), Dynamically configurable portable computer system.
  18. Kimura Toshiyuki (Kawagoe JPX) Yamazaki Youichi (Kawagoe JPX) Nonaka Yoshiya (Kawagoe JPX) Go Yasunao (Kawagoe JPX) Endo Fumio (Kawagoe JPX) Komata Hiroyuki (Kawagoe JPX) Syoji Mitsuo (Kawagoe JPX), Electronic unit operable in conjunction with body unit.
  19. Poret Mark (Mesa AZ) McKinley Jeanne (Chandler AZ), In-circuit emulator.
  20. Suzuki Naoshi (Kanagawa JPX) Uno Shunya (Machida JPX), Information processing system having power saving control of the processor clock.
  21. Little Wendell L. (Carrollton TX), Integrated circuit with watchdog timer and sleep control logic which places IC and watchdog timer into sleep mode.
  22. Yorimoto Yoshikazu (Tokyo JPX) Takahashi Masashi (Tokyo JPX) Hirano Seiji (Tokyo JPX), Integrated-circuit card with active mode and low power mode.
  23. Raasch Charles F. (El Toro CA) Kim Jason S. M. (Los Angeles CA), Internal interrupt controller for a peripheral controller.
  24. Bartling James E. (Dallas TX) Little Wendell L. (Denton TX) Deierling Kevin E. (Dallas TX), Isolation gates to permit selective power-downs within a closely-coupled multi-chip system.
  25. Jones Steven W. (Wood Dale IL) Alifen Chandra (Hoffman Estates IL), Line power failure scheme for a gaming device.
  26. Cole James F. (Palo Alto CA) McNamara James H. (Santa Cruz CA), Low-power, standby mode computer.
  27. Cole James F. (Palo Alto CA) McNamara James H. (Santa Cruz CA), Low-power, standby mode computer.
  28. Nishimura Kosuke (Yamatokoriyama JPX), Memory contents confirmation.
  29. Belt Steven L. (Stevensville MI) Ruthenbeck Mark A. (Lincoln Township ; Berrien County MI) Foster Mark J. (Lincoln Township ; Berrien County MI) Barnes Brian C. (Benton Township ; Berrien County MI) , Method and apparatus facilitating communication between two keyboards and a single processor.
  30. Fakruddin Saifee (St. Joseph MI) Foster Mark J. (Stevensville MI), Method and apparatus for battery-power management using load-compensation monitoring of battery discharge.
  31. Letwin James (Kirkland WA), Method and operating system for executing programs in a multi-mode microprocessor.
  32. Watanabe Minoru (Tokyo JPX), Microcomputer which enters sleep mode for a predetermined period of time on response to an activity of an input/output d.
  33. Arroyo Ronald X. (Elgin TX) Hanna James T. (Austin TX), Multi-frequency clock generation with low state coincidence upon latching.
  34. Yurchenco James R. (Palo Alto CA), Multiple independent input peripherals.
  35. Hirano Takaaki (Nara JPX) Kamuro Setsufumi (Yamatokoriyama JPX) Yamaguchi Akira (Nara JPX) Tanimoto Junichi (Tenri JPX) Okada Mikiro (Nara JPX), Peripheral unit for a microprocessor system.
  36. Kobayashi Takaichi (Itsukaichi JPX), Personal computer having condition indicator.
  37. Murez James D. (Santa Monica CA), Portable computer enclosure.
  38. Perry Richard A. (Charlotte NC) Stant Vernon L. (Richmond VA), Power conservation in microprocessor controlled devices.
  39. Zato Thomas J. (Palatine IL), Power loss compensation for programmable memory control system.
  40. Smith R. Steven (Saratoga CA) Hanlon Mike S. (San Jose CA) Bailey Robert L. (San Jose CA), Power management for a laptop computer with slow and sleep modes.
  41. Juzswik David L. (Dearborn Heights MI) Webb Nathaniel (Detroit MI) Floyd William M. (Livonia MI), Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system ina.
  42. Mori Shosuke (Tokyo JPX), Processor having plural initial loading programs for loading different operating systems.
  43. Watts ; Jr. LaVaughn F. (Temple TX) Wallace Steven J. (Temple TX), Real-time power conservation for portable computers.
  44. Niijima Shinji (Tokyo JPX), Single-chip mircocomputer with clock-signal switching function which can disable a high-speed oscillator to reduce power.
  45. Nocilini, John D.; Sharp, Ronald E.; Cuadra, Emilio J., Stanby mode controller utilizing microprocessor.
  46. Nguyen Au H. (Santa Clara CA) Gollabinnie Aurav R. (San Jose CA), Suspend/resume apparatus and method for reducing power consumption in battery powered computers.
  47. Lee Robert H. J. (Palo Alto CA) Kenny John D. (Sunnyvale CA), Switchable clock circuit for microprocessors to thereby save power.
  48. Chang Bo E. (22 Yearling Ct. Rockville MD 20850), Three layered laptop computer.
  49. Kardach James (San Jose CA) Mathews Gregory (Cupertino CA) Nguyen Cau (Milpitas CA) Cho Sung S. (Sunnyvale CA) Sivamani Kameswaran (Sunnyvale CA) Vannier David (Cupertino CA) Wong Shing (Cupertino CA, Transparent system interrupt.
  50. Byrd Kerry (Falls Church VA), Work-saving system for preventing loss in a computer due to power interruption.
  51. Alley Lynn D. (Riverton UT) Alley Stephen W. (Bountiful UT) Sadlier William K. (Salt Lake City UT) Burton Richard A. (Salt Lake City UT), Wrap-around auxiliary keyboard.
  52. Director Dennis (3116 Central St. Evanston IL 60201), Write protect control circuit for computer hard disc systems.

이 특허를 인용한 특허 (4)

  1. Lin, Richard S.; Jabori, Monji G.; Barlow, Dallas M., Computer protection system and method.
  2. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
  3. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
  4. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
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