초록 ▼

This invention deals with various circuits using transistors having two different threshold voltages designated high threshold voltage (HVT) and low threshold voltage (LVT). These circuits employ the know faster response time of LVT transistors while substantially avoiding the known greater leakage

This invention deals with various circuits using transistors having two different threshold voltages designated high threshold voltage (HVT) and low threshold voltage (LVT). These circuits employ the know faster response time of LVT transistors while substantially avoiding the known greater leakage current of LVT transistors. A two input multiplexer includes two transmission gates driven in opposite phases by a selection control signal. One transmission gate, preferably the transmission gate most often selected, includes LVT transistors while the other transmission gate includes HVT transistors. A hybrid threshold voltage D flip-flop circuit employs LVT transistors in input transmission gates of both a master latch and a slave latch. In a conventional circuit, the output invertor of the slave latch also includes LVT transistors. In a split slave dual path circuit, the intermediate inverter also includes LVT transistors. In a push-pull output register, the inverter and transmission gate of the push-pull circuit may include LVT transistors. In a first alternative, only the transmission gates in the push-pull circuit and the slave latch include LVT transistors. In a second alternative, only the inverter on the push-pull circuit and the output inverter of the slave latch include LVT transistors. In a third alternative, the push-pull circuit is a hybrid threshold voltage tri-state inverter.

대표청구항 ▼

[ What is claimed is:] [1.] A D flip-flop circuit having an input and an output comprising:a master latch includinga first master transmission gate clocked in a first phase having an input serving as input to said master latch and to said input of said D flip-flop circuit and an output, said first m

[ What is claimed is:] [1.] A D flip-flop circuit having an input and an output comprising:a master latch includinga first master transmission gate clocked in a first phase having an input serving as input to said master latch and to said input of said D flip-flop circuit and an output, said first master transmission gate constructed of transistors having a first threshold voltage,a first master latch inverter having an input connected to said output of said first master transmission gate and an output serving as output of said master latch, said first master latch inverter constructed of transistors having a second threshold voltage higher than said first threshold voltage,a second master latch inverter having an input connected to said output of said first master latch inverter and an output connected to said input of said first master latch inverter, said second master latch inverter constructed of transistors having said second threshold voltage; and a slave latch includinga first slave transmission gate clocked in a second phase opposite to said first phase having an input connected to said output of said master latch and an output, said first slave transmission gate constructed of transistors having said first threshold voltage,a first slave latch inverter having an input connected to said output of said first slave transmission gate and an output serving as output of said slave latch and said output of said D flip-flop circuit, said first slave latch inverter constructed of transistors having said first threshold voltage,a second slave latch inverter having an input connected to said output of said first slave latch inverter and an output connected to said input of said first slave latch inverter, said second slave latch inverter constructed of transistors having said second threshold voltage.