초록 ▼

A variable delay circuit for a semiconductor memory device includes an input buffer for converting a digital input signal to an analog signal and buffering the resultant analog signal, an analog delay unit for delaying the analog signal outputted from the input buffer unit for a certain time, and an

A variable delay circuit for a semiconductor memory device includes an input buffer for converting a digital input signal to an analog signal and buffering the resultant analog signal, an analog delay unit for delaying the analog signal outputted from the input buffer unit for a certain time, and an output buffer unit for converting the delayed analog signal to a digital signal and buffering the resultant digital signal. The analog delay unit is composed of a CMOS inverter, a plurality of operational transconductance amplifier-capacitor delay elements, and an output inverter, to form a second-order Bessel filter. An O.T.A and an inverter may be additionally provided between the plurality of O.T.A.'s for thereby decreasing a parasitic effect of the capacitors connected to the outputs of each of the plurality of O.T.A.'s in the analog delay unit. The delay circuit serves to obtain a desired delay time by varying a control voltage irrespective of unstable time delay values of components caused by the fabrication process.

대표청구항 ▼

[ What is claimed is:] [1.] A variable delay circuit, comprising:an input buffer that buffers an input signal to output a first signal;a delay circuit that delays the first signal provided from the input buffer for a prescribed time, wherein the delay circuit comprises,a plurality of operational tra

[ What is claimed is:] [1.] A variable delay circuit, comprising:an input buffer that buffers an input signal to output a first signal;a delay circuit that delays the first signal provided from the input buffer for a prescribed time, wherein the delay circuit comprises,a plurality of operational transconductance amplifiers (OTAs) coupled in series to delay the first signal in accordance with an applied control signal,a plurality of capacitors, wherein each of the capacitors is coupled to an output terminal of a corresponding one of the OTAs,at least one compensating unit, wherein each of the compensating units is coupled to the output terminal of a corresponding one of the plurality of OTAs to reduce a parasitic effect in the first signal delayed for the prescribed time; andan output buffer that buffers the first signal delayed for the prescribed time.