초록 ▼

A system and method for altering the appearance of interference in a video signal caused by spurious interference generated by repeated high speed digital memory write operations affecting video processing in analog circuitry in thereceiver. In one particular embodiment, a picture-in-picture televis

A system and method for altering the appearance of interference in a video signal caused by spurious interference generated by repeated high speed digital memory write operations affecting video processing in analog circuitry in thereceiver. In one particular embodiment, a picture-in-picture television receiver is provided wherein both the main and sub-pictures are processed on a single IC including analog processing circuitry, as well as a small picture memory array to which small picture video samples are repeatedly being written. The visibility of spurious interference in the picture is reduced by periodically altering the clock timing during the repetitive high speed writing operation to redistribute the interference so as to be less noticeable to the television viewer.

대표청구항 ▼

[ What is claimed is:] [1.] A television product with reduced visibility of spurious interference in the output video signal, comprising:a display for displaying an output video signal;at least one video input for receiving at least one input video signal;a fast memory for storing video picture info

[ What is claimed is:] [1.] A television product with reduced visibility of spurious interference in the output video signal, comprising:a display for displaying an output video signal;at least one video input for receiving at least one input video signal;a fast memory for storing video picture information;an integrated circuit for processing the at least one input video signal, said integrated circuit including,analog circuitry for processing the video signal,a high speed writing circuit for repetitively writing video picture information to said fast memory,a clock for producing a clock timing signal,a write timing modifier connected to said clock to receive said clock timing signal from said clock, said write timing modifier including circuitry to periodically alter said clock timing signal at least once per every two frames of the output video, and for providing said altered clock timing signal to said high speed writing circuit, whereby said periodically altered clock timing signal causes a periodic shift in said writing to said fast memory thus producing an altered interference pattern in the output video signal,wherein, said write timing modifier periodically delays said clock timing signal whereby changing the phase of said clock timing signal, andwherein said write timing modifier includes a second timing signal and a detector for detecting said second timing signal, and wherein said detector additionally generates square waves in response to said timing signal.