초록 ▼

A first precharge circuit precharges a bit line to an equalization voltage during precharging operations and is disabled during charge sharing operations floating the bit line. A second precharge circuit precharges a bit line bar to an equalization voltage during precharging and charge sharing opera

A first precharge circuit precharges a bit line to an equalization voltage during precharging operations and is disabled during charge sharing operations floating the bit line. A second precharge circuit precharges a bit line bar to an equalization voltage during precharging and charge sharing operations. Since the bit line is floated during charge sharing operations, and the bit line bar is continually precharged to an equalization voltage level, variation of the bit line bar voltage level due to a charge coupling between the bit line and the bit line bar during charge sharing is prevented. The difference in a level between the bit line and the bit line bar after the charge sharing can be detected by a sense and amplification circuit.

대표청구항 ▼

[ What is claimed is:] [1.] A bit line control circuit for a semiconductor memory device comprising:a bit line and a bit line bar;an equalization power line for supplying equalization voltage;a first precharge circuit connected between the equalization power line and the bit line for precharging the

[ What is claimed is:] [1.] A bit line control circuit for a semiconductor memory device comprising:a bit line and a bit line bar;an equalization power line for supplying equalization voltage;a first precharge circuit connected between the equalization power line and the bit line for precharging the bit line to the equalization voltage during a precharge operation, the first precharge circuit floating the bit line during a charge sharing operation; anda second precharge circuit connected between the equalization power line and the bit line bar and separately enabled from the first precharge circuit for precharging the bit line bar to the equalization voltage during the precharging operation and during the charge sharing operation at a same time the first precharge circuit is floating the bit line.