초록 ▼

A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external

A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external electrical connections for I/Os and power. And fuses are used in the underlying insulating layers to remove redundant defective circuit elements and thereby repair defective chips. It is desirable (cost effective) to etch the contact openings in the passivation layer to the bonding pads near the top surface on the chip and to concurrently etch the much deeper fuse openings in the thick underlying insulating layers over the fuses. However, because of the difference in etch depth of the two types of openings, the bonding pads composed of Al/Cu are generally overetched causing bond-pad reliability problems. This invention uses a novel process in which a capping layer, having a low etch rate, is formed on the bonding pads to prevent overetching while the fuse openings are etched to the desired depth in the thicker insulating layers.

대표청구항 ▼

[ What is claimed is:] [1.] A method for fabricating bonding pads for integrated circuits comprising the steps of:providing a semiconductor substrate having devices formed from a patterned polysilicon layer in device areas that are surrounded by a field oxide isolation, and further having a multilev

[ What is claimed is:] [1.] A method for fabricating bonding pads for integrated circuits comprising the steps of:providing a semiconductor substrate having devices formed from a patterned polysilicon layer in device areas that are surrounded by a field oxide isolation, and further having a multilevel of patterned conducting layers, with alternating insulating layers having interconnecting conducting plugs to provide electrical interconnections between said patterned conducting layers for said devices;depositing a bond-pad conducting layer over the topmost insulating layer of said multilevel and over said interconnecting conducting plugs;depositing a capping layer over said bond-pad conducting layer to provide an etch-stop layer;patterning said capping layer and said bond-pad conducting layer to form bonding pads for integrated circuits;depositing a passivation layer over said bonding pads;selectively etching contact openings in said passivation layer over said bonding pads wherein said capping layer prevents said selective etching from etching said bonding pads, while concurrently etching fuse openings through said passivation layer and said insulating layers of said multilevel and leaving a portion of said insulating layers over portions of said underlying patterned polysilicon layer that serve as fuses;selectively etching said capping layer in said contact openings to complete said bonding pads and said fuse openings for said integrated circuits.