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Bond pad design for integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0072369 (1998-05-04)
발명자 / 주소
  • Chittipeddi Sailesh
  • Ryan Vivian
출원인 / 주소
  • Lucent Technologies Inc.
인용정보 피인용 횟수 : 57  인용 특허 : 5

초록

The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support

대표청구항

[ What is claimed is:] [1.] For use in an integrated circuit having a bond pad located thereon, a bond pad support structure, comprising:a conductive metal first bond pad support layer located below said bond pad and having a plurality of openings formed therein, each of said plurality of openings f

이 특허에 인용된 특허 (5)

  1. Chittipeddi Sailesh ; Cochran William Thomas ; Smooha Yehuda, Integrated circuit with active devices under bond pads.
  2. Sato Hisakatsu,JPX, Semiconductor device having a multi-latered wiring structure.
  3. Matsumoto Hiroshi (Hyogo JPX), Semiconductor device in which wiring layer is formed below bonding pad.
  4. Nozaki Masahiko (Hyogo JPX), Semiconductor device structure including multiple interconnection layers with interlayer insulating films.
  5. Abe Masahiro (Yokohama JPX) Aoyama Masaharu (Fujisawa JPX) Ajima Takashi (Kamakura JPX) Yonezawa Toshio (Yokosuka JPX), Semiconductor device with an improved bonding section.

이 특허를 인용한 특허 (57)

  1. Brett H. Engel ; Vincent James McGahay ; Henry Atkinson Nye, III, Bond pad structure and method for reduced downward force wirebonding.
  2. Leobandung, Effendi, Chip with programmable shelf life.
  3. Leobandung, Effendi, Chip with programmable shelf life.
  4. Efland,Taylor R., Circuit method integrating the power distribution functions of the circuits and leadframes into the chip surface.
  5. Efland, Taylor R., Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface.
  6. Shu, William Kuang-Hua, Die pad crack absorption system and method for integrated circuit chip fabrication.
  7. Jones, Jeffrey K.; Szymanowski, Margaret A.; Miera, Michele L.; Ren, Xiaowei; Burger, Wayne R.; Bennett, Mark A.; Kerr, Colin, Electronic elements and devices with trench under bond pad feature.
  8. Mukul Saran ; Charles A. Martin ; Ronald H. Cox, Fine pitch system and method for reinforcing bond pads in semiconductor devices.
  9. Saran, Mukul; Martin, Charles A.; Cox, Ronald H., Fine pitch system and method for reinforcing bond pads in semiconductor devices.
  10. Schroen Walter H. ; Archer Judith S. ; Terrill Robert E., Fully hermetic semiconductor chip, including sealed edge sides.
  11. Lee Hyae-ryoung,KRX, Integrated circuit bonding pads including closed vias and closed conductive patterns.
  12. Lee, Soo-cheol; Ahn, Jong-hyon; Son, Kyoung-mok; Shin, Heon-jong; Lee, Hyae-ryoung; Kim, Young-pill; Jung, Moo-jin; Wang, Son-jong; Yoo, Jae-Cheol, Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same.
  13. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  14. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  15. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  16. Benedetto Vigna IT; Enrico Maria Alfonso Ravanelli IT, Integrated electronic device comprising a mechanical stress protection structure.
  17. Furukawa, Toshiharu; Hakey, Mark Charles; Holmes, Steven J.; Horak, David V.; Koburger, III, Charles William; Lam, Chung Hon, Layout and process to contact sub-lithographic structures.
  18. Ker, Ming-Dou; Jiang, Hsin-Chin, Low-capacitance bonding pad for semiconductor device.
  19. Ming-Dou Ker TW; Hsin-Chin Jiang TW, Low-capacitance bonding pad for semiconductor device.
  20. Yiu Ho-Yin,TWX ; Wu Lin-June,TWX ; Chen Bor-Cheng,TWX ; Horng J. H.,TWX, Method for fabricating a stress buffered bond pad.
  21. Lee,Jin Hyuk; Kim,Gu Sung; Lee,Dong Ho; Jang,Dong Hyeon, Method for manufacturing a wafer level chip scale package.
  22. Sabin, Gregory D.; Gross, William J.; Chang, Jung-Yueh, Method for placing active circuits beneath active bonding pads.
  23. Sabin, Gregory D.; Gross, William J.; Chang, Jung-Yueh, Method for placing active circuits beneath active bonding pads.
  24. Goebel, Thomas; Kaltalioglu, Erdem; Kim, Sun-Oo, Method of forming support structures for semiconductor devices.
  25. Jones, Jeffrey K.; Szymanowski, Margaret A.; Miera, Michele L.; Ren, Xiaowei; Burger, Wayne R.; Bennett, Mark A.; Kerr, Colin, Methods for forming an RF device with trench under bond pad feature.
  26. Soo-cheol Lee KR; Jong-hyon Ahn KR; Hyae-ryoung Lee KR, Methods of fabricating integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein.
  27. Singh,Inderjit; Marks,Howard Lee; Greco,Joseph David, Pad over active circuit system and method with frame support structure.
  28. Singh,Inderjit; Marks,Howard Lee; Greco,Joseph David, Pad over active circuit system and method with meshed support structure.
  29. Hunter, Stevan G.; Rasmussen, Bryce A.; Ruud, Troy L., Pad over interconnect pad structure design.
  30. Ikuta,Teruhisa; Ogura,Hiroyoshi; Sato,Yoshinobu; Terashita,Toru; Ichijo,Hisao, Semiconductor device.
  31. Kanzaki, Teruaki; Deguchi, Yoshinori; Miki, Kazunobu, Semiconductor device.
  32. Kanzaki, Teruaki; Deguchi, Yoshinori; Miki, Kazunobu, Semiconductor device.
  33. Shigeru Harada JP; Takeru Matsuoka JP; Hiroki Takewaka JP, Semiconductor device and fabrication process therefor.
  34. Watanabe, Kenichi; Ikeda, Masanobu; Kimura, Takahiro, Semiconductor device and method for manufacturing the same.
  35. Watanabe, Kenichi; Ikeda, Masanobu; Kimura, Takahiro, Semiconductor device and method for manufacturing the same.
  36. Watanabe,Kenichi, Semiconductor device for preventing defective filling of interconnection and cracking of insulating film.
  37. Yamazaki, Yasushi, Semiconductor device having a bonding pad structure including an annular contact.
  38. Hirano, Hiroshige; Ota, Yukitoshi; Itoh, Yutaka, Semiconductor device having a pad.
  39. Yao, Ze-Qiang; Yin, Fayou; Shang, Xiaodan, Semiconductor device having conductive bump with improved reliability.
  40. Oda, Noriaki, Semiconductor device with bonding pad support structure.
  41. Oda,Noriaki, Semiconductor device with bonding pad support structure.
  42. Saito,Hitoshi, Semiconductor element and manufacturing method thereof.
  43. Saito,Hitoshi, Semiconductor element and manufacturing method thereof.
  44. Maeda, Jun, Semiconductor integrated circuit having connection pads over active elements.
  45. Zhao, Bin, Structure for bonding pad and method for its fabrication.
  46. Goebel, Thomas; Kaltalioglu, Erdem; Kim, Sun Oo, Support structures for semiconductor devices.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  55. Ashton, Robert A.; Lytle, Steven A.; Roby, Mary D.; Thoma, Morgan J.; Vitkavage, Daniel J., Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof.
  56. Li, Yuan; Nath, Som; Van Dort, Maarten Jeroen, Via network structures and method therefor.
  57. Li, Yuan; Nath, Som; van Dort, Maarten, Via network structures and method therefor.
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