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Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method the 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/28
출원번호 US-0686763 (1996-07-26)
발명자 / 주소
  • Suwanai Naokatsu,JPX
  • Fujioka Yasuhide,JPX
출원인 / 주소
  • Hitachi, Ltd., JPX
대리인 / 주소
    Antonelli, Terry, Stout & Kraus, LLP.
인용정보 피인용 횟수 : 37  인용 특허 : 3

초록

A semiconductor integrated circuit device is provided in which an interlayer insulation film deposited on a semiconductor chip includes a boron-containing silicon oxide film and a second film deposited on the boron-containing silicon oxide film. A guard ring is disposed adjacent to the periphery of

대표청구항

[ What is claimed is:] [6.] A semiconductor integrated circuit device comprising:a semiconductor substrate having a first region which is a peripheral portion of a main surface and a second region inside of the first region in said main surface,a plurality of MISFETs each formed in the second region

이 특허에 인용된 특허 (3)

  1. Herman Thomas (Redondo Beach CA) Lidow Alexander (Manhattan Beach CA), Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions.
  2. Shirai Kenichi (Yokohama JPX) Shibahara Satoshi (Tokyo JPX), Semiconductor device having a moisture barrier around periphery of device.
  3. Morita Naoyuki (Nagano JPX), Semiconductor device with interlayer insulating film covering the chip scribe lines.

이 특허를 인용한 특허 (37)

  1. Huh, Jeong-Uk; Balseanu, Mihaela; Xia, Li-Qun; Witty, Derek R.; M'Saad, Hichem, Boron derived materials deposition method.
  2. Balseanu, Mihaela; Bencher, Christopher D.; Chen, Yongmei; Miao, Li Yan; Nguyen, Victor; Roflox, Isabelita; Xia, Li-Qun; Witty, Derek R., Boron nitride and boron-nitride derived materials deposition method.
  3. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Luce, Stephen E.; McDevitt, Thomas L.; Motsiff, William T.; Pouliot, Mark J.; Robbins, Jennifer C., Crack stop for low K dielectrics.
  4. Daubenspeck,Timothy H.; Gambino,Jeffrey P.; Luce,Stephen E.; McDevitt,Thomas L.; Motsiff,William T.; Pouliot,Mark J.; Robbins,Jennifer C., Crack stop for low K dielectrics.
  5. Souza, Theresa R.; Nelson, Larre, Electrical test probes and methods of making the same.
  6. Minn, Eun-young; Park, Young-hoon; Lee, Chi-hoon; Han, Myoung-hee, Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same.
  7. Abbott Donald C. ; Moehle Paul R., Leadframes with selective palladium plating.
  8. Sakai,Norio; Iida,Kazuhiro, Manufacturing method for multilayer ceramic elements.
  9. Nguyen, Victor; Chen, Yi; Balseanu, Mihaela; Roflox, Isabelita; Xia, Li-Qun; Witty, Derek R, Method for depositing boron-rich films for lithographic mask applications.
  10. Togo, Kenji; Sano, Hiroaki, Method for manufacturing semiconductor device and semiconductor wafer.
  11. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  12. Miyaki, Yoshinori; Suzuki, Hiromichi; Suzuki, Kazunari; Nishita, Takafumi; Ito, Fujio; Tsubosaki, Kunihiro; Kameoka, Akihiko; Nishi, Kunihiko, Method of manufacturing a semiconductor device.
  13. Miyaki,Yoshinori; Suzuki,Hiromichi; Suzuki,Kazunari; Nishita,Takafumi; Ito,Fujio; Tsubosaki,Kunihiro; Kameoka,Akihiko; Nishi,Kunihiko, Method of manufacturing a semiconductor device.
  14. Sakai, Norio; Iida, Kazuhiro, Multilayer integrated substrate and manufacturing method for multilayer ceramic element.
  15. Patrizia Sonego IT; Maurizio Bacchetta IT, Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices.
  16. Wang, Chien-Jung; Lin, Jian-Hong, Seal ring structures with reduced moisture-induced reliability degradation.
  17. Wang, Chien-Jung; Lin, Jian-Hong, Seal ring structures with reduced moisture-induced reliability degradation.
  18. Furusawa, Takeshi; Miura, Noriko; Goto, Kinya; Matsuura, Masazumi, Semiconductor chip with seal ring and sacrificial corner pattern.
  19. Furusawa, Takeshi; Miura, Noriko; Goto, Kinya; Matsuura, Masazumi, Semiconductor chip with seal ring and sacrificial corner pattern.
  20. Nakamura,Naofumi; Matsunaga,Noriaki; Ito,Sachiyo; Hasunuma,Masahiko; Nishioka,Takeshi, Semiconductor device.
  21. Tsutsue, Makoto; Utsumi, Masaki, Semiconductor device.
  22. Tsutsue, Makoto; Utsumi, Masaki, Semiconductor device.
  23. Tsutsue, Makoto; Utsumi, Masaki, Semiconductor device.
  24. Tsutsue, Makoto; Utsumi, Masaki, Semiconductor device.
  25. Sakoh, Takashi; Toda, Mami, Semiconductor device and method for manufacturing same.
  26. Eimori, Takahisa, Semiconductor device and method of fabricating the same.
  27. Akiyama, Kazutaka, Semiconductor device and semiconductor device manufacturing method.
  28. Kim, Byung yoon; Lee, Won seong; Park, Young woo, Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area.
  29. Motsiff, William T.; Shapiro, Michael J., Semiconductor device with internal heat dissipation.
  30. Narumi Ohkawa JP, Semiconductor device with metal silicide film on partial area of substrate surface and its manufacture method.
  31. Eimori,Takahisa, Semiconductor device with multiple layer insulating film.
  32. Tomita, Kazuo, Semiconductor device with seal ring.
  33. Yoon, Junho; Min, Gyungjin; Park, Jaehong; Jang, Yongmoon; Han, Je-Woo, Semiconductor devices including a support for an electrode and methods of forming semiconductor devices including a support for an electrode.
  34. Yoon, Junho; Min, Gyungjin; Park, Jaehong; Jang, Yongmoon; Han, Je-Woo, Semiconductor devices including a support for an electrode and methods of forming semiconductor devices including a support for an electrode.
  35. Kawashima, Hiroyuki, Solid-state imaging device, method for manufacturing solid-state imaging device, method for manufacturing solid-state imaging element, and semiconductor device.
  36. Wang, Yung-Yao; Chiou, Ying-Han; Wang, Ling-Sung, Stress tuning for reducing wafer warpage.
  37. Wang, Yung-Yao; Chiou, Ying-Han; Wang, Ling-Sung, Stress tuning for reducing wafer warpage.
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