초록 ▼

A circuit arrangement for a flip chip utilizes fixed potential shield traces between various signal traces in a redistribution layer to decrease coupling impedances and crosstalk within the layer. In particular, by orienting a fixed potential shield trace between a pair of signal traces and/or betwe

A circuit arrangement for a flip chip utilizes fixed potential shield traces between various signal traces in a redistribution layer to decrease coupling impedances and crosstalk within the layer. In particular, by orienting a fixed potential shield trace between a pair of signal traces and/or between a pair of differential trace pairs, capacitive coupling between the traces is greatly reduced, thereby permitting the signal traces to be routed closer to one another than would be possible if the shield trace was omitted. Often, minimum line width and spacing design rules may be met to ensure maximum circuit density for the redistribution layer and the associated device interconnections, and without concern for excessive adverse effects due to capacitive coupling between traces in the redistribution layer.

대표청구항 ▼

[ What is claimed is:] [1.] A circuit arrangement for a flip chip, comprising:(a) a logic circuit including a plurality of input/output (I/O) ports and disposed in at least one logic circuit layer; and(b) a redistribution circuit arrangement disposed in a redistribution layer, the redistribution cir

[ What is claimed is:] [1.] A circuit arrangement for a flip chip, comprising:(a) a logic circuit including a plurality of input/output (I/O) ports and disposed in at least one logic circuit layer; and(b) a redistribution circuit arrangement disposed in a redistribution layer, the redistribution circuit arrangement including:(1) a plurality of pads arranged in a predetermined pattern;(2) a plurality of signal redistribution traces, each signal redistribution trace electrically connecting an I/O port to a pad; and(3) a plurality of shield traces, wherein each non-differential pair of adjacent signal redistribution traces from the plurality of signal redistribution traces has interposed therebetween an associated shield trace from the plurality of shield traces, with each shield trace connected to a fixed potential and operatively configured to reduce capacitive coupling between the pair of adjacent signal redistribution traces associated therewith.