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Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0932614 (1997-09-17)
발명자 / 주소
  • Zhao Joe W.
  • Catabay Wilbur G.
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Taylor
인용정보 피인용 횟수 : 23  인용 특허 : 25

초록

The invention comprises an integrated circuit structure, and a process for making same, comprising a via/contact opening in a dielectric layer; a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 Angstroms, on the sidewall and bottom surface

대표청구항

[ Having thus described the invention what is claimed is:] [1.] An integrated circuit structure comprising:a) a via/contact opening in a dielectric layer over a semiconductor substrate;b) a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 A

이 특허에 인용된 특허 (25)

  1. Thalapaneni Gurunada (Union City CA), Barrier metal contact architecture.
  2. Yu Chang (2801 Stewart Ave. Boise ID 83702) Doan Trung T. (1574 Shenandoah Dr. Boise ID 83712), Bilayer barrier metal method for obtaining 100% step-coverage in contact vias without junction degradation.
  3. Bai Gang ; Fraser David B., Diffusion barrier for electrical interconnects in an integrated circuit.
  4. Fujita Toshiaki (Chiba JPX), Metal CVD process with post-deposition removal of alloy produced by CVD process.
  5. Marangon Maria S. (Naviglio ITX) Marmiroli Andrea (Alzano Lombardo ITX) Desanti Giorgio (Milan ITX), Metallization over tungsten plugs.
  6. Sun Shih W. (Austin TX) Lee Jen-Jiang (Austin TX), Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process.
  7. Liou Fu-Tai (Carrollton TX) Miller Robert O. (The Colony TX) Farohani Mohammed M. (Carrollton TX) Han Yu-Pin (Dallas TX), Method for forming a contact/VIA.
  8. Sumi Hirofumi (Kanagawa JPX), Method for forming barrier metal structure.
  9. Somekh Sasson (Los Altos Hills CA) Nulman Jaim (Palo Alto CA) Chang Mei (Cupertino CA), Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer.
  10. Somekh Sasson (Los Altos Hills CA) Nulman Jaim (Palo Alto CA) Chang Mei (Cupertino CA), Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer.
  11. Kim Choon H. (Bubaleub KRX), Method for forming tungsten plug for metal wiring.
  12. Mueller Mark A. (San Jose CA) Guo Xin (Mountain View CA) Egermeier John C. (Santa Clara CA), Method for in-situ cleaning a Ti target in a Ti +TiN coating process.
  13. Pintchovski Faivel (Austin TX) Tobin Philip J. (Austin TX), Method for making a w/tin contact.
  14. Harada Shigeru (Hyogo JPX) Ishimaru Kazuhiro (Hyogo JPX) Hagi Kimio (Hyogo JPX), Method of forming an interconnection structure.
  15. Yamamoto Hiroshi (Chiba JPX) Takeyasu Nobuyuki (Chiba JPX) Ohta Tomohiro (Urayasu JPX), Method of forming multilayered wiring structure in semiconductor device.
  16. Chen Shih-Chang (Tokyo JPX), Method of making semiconductor device comprising a titanium nitride film.
  17. Sumi Hirofumi (Kanagawa JPX), Method of manufacturing semiconductor device by forming barrier metal layer between substrate and wiring layer.
  18. Chen Mao-Chieh (Hsinchu TWX) Yang Fann-Mei (Shanhua Town TWX), Process for fabricating device having titanium-tungsten barrier layer and silicide layer contacted shallow junction simu.
  19. Lifshitz Nadia (1591 Longhill Rd. Millington NJ 07946) Schutz Ronald J. (14 Upper Warren Way Warren NJ 07060), Process for fabricating integrated circuits having shallow junctions.
  20. Gelatos Avgerinos V. (Austin TX) Fiordalice Robert W. (Austin TX), Process for forming copper interconnect structure.
  21. Tsai Nun-Sian (Hsinchu TWX) Huang Yung-Sheng (Hsin-Chu TWX), Process for removing seams in tungsten plugs.
  22. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD.
  23. Gn Fang Hong (Singapore SGX) Ramamoorthy Sekar (Singapore SGX) Chan Lap (Singapore SGX) Wei Che-Chia (Singapore SGX), Semiconductor contact metallization.
  24. Chung Henry W. (Cupertino CA) Yao Tsui Y. (Saratoga CA), Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier ma.
  25. Romero Jeremias D. (San Jose CA) Fatemi Homi (Los Altos Hills CA) Delenia Eugene A. (Gilroy CA) Khan Muhib M. (San Jose CA), TiW barrier metal process.

이 특허를 인용한 특허 (23)

  1. Gurtej Sandhu ; Garo J. Derderian, ALD method to improve surface coverage.
  2. Sandhu, Gurtej; Derderian, Garo J., ALD method to improve surface coverage.
  3. Brennan William S., CVD Tin Barrier process with improved contact resistance.
  4. Sandhu, Gurtej; Derderian, Garo J., Film composition.
  5. Tanaka, Shun-ichiro; Wakayama, Yutaka, Fine protuberance structure and method of production thereof.
  6. Sandhu, Gurtej S.; Iyer, Ravi, Integrated circuitry.
  7. Sandhu, Gurtej S.; Iyer, Ravi, Integrated circuitry.
  8. Sandhu, Sukesh, Isolation regions.
  9. Sandhu, Sukesh, Isolation regions and their formation.
  10. Cheng, Chuan-cheng; Lakshminarayanan, Sethuraman; Wright, Peter J.; Ying, Hong, Low resistance metal interconnect lines and a process for fabricating them.
  11. Seong-Dai Jang KR; Jin-Ho Choi KR, Method of forming a tungsten plug in a semiconductor device.
  12. Wang Shulin ; Xi Ming ; Lando Zvi ; Chang Mei, Method of titanium/titanium nitride integration.
  13. Wang Shulin ; Xi Ming ; Lando Zvi ; Chang Mei, Method of titanium/titanium nitride integration.
  14. Lu, Xinliang; Jian, Ping; Yoo, Jong Hyun; Lai, Ken Kaung; Mak, Alfred W.; Jackson, Robert L.; Xi, Ming, Pulsed deposition process for tungsten nucleation.
  15. Lu,Xinliang; Jian,Ping; Yoo,Jong Hyun; Lai,Ken Kaung; Mak,Alfred W.; Jackson,Robert L.; Xi,Ming, Pulsed nucleation deposition of tungsten layers.
  16. Hampp, Roland, Self aligned silicided contacts.
  17. Hampp, Roland, Self aligned silicided contacts.
  18. Hampp, Roland, Self aligned silicided contacts.
  19. Sandhu, Gurtej; Derderian, Garo J., Semiconductor device with novel film composition.
  20. Sandhu, Gurtej; Derderian, Garo J., Semiconductor device with novel film composition.
  21. Pramanick Shekhar ; Brown Dirk ; Nogami Takeshi, Semiconductor interconnect interface processing by pulse laser anneal.
  22. Sandhu, Gurtej S.; Iyer, Ravi, Semiconductor processing methods and integrated circuitry.
  23. Uzoh Cyprian E., Triple damascence tungsten-copper interconnect structure.
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