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Network configuration of programmable circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/177
  • G06F-019/00
출원번호 US-0023334 (1998-02-13)
발명자 / 주소
  • Guccione Steven A.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Cartier
인용정보 피인용 횟수 : 46  인용 특허 : 8

초록

An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configurat

대표청구항

[ What is claimed is:] [1.] An interactive software tool for writing data into a programmable logic device, the tool comprising:means for accessing via a network server a hardware device designed to interface with the programmable logic device;interactive means for specifying data to be written to t

이 특허에 인용된 특허 (8)

  1. Sample Stephen P. (Mountain View CA) D\Amour Michael R. (Los Altos Hills CA) Payne Thomas S. (Union City CA), Apparatus for emulation of electronic hardware system.
  2. Beyda William J., Autoconfigurable method and system having automated downloading.
  3. Casselman Steven M., Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed.
  4. Ahlin, Leo; Kawan, Joseph C., Distributed-intelligence computer system including remotely reconfigurable, telephone-type user terminal.
  5. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  6. Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.
  7. Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
  8. Aldebert Jeane-Paul,FRX ; Basso Claude,FRX ; Calvignac Jean,FRX ; Chemla Paul,FRX ; Orsatti Daniel,FRX ; Verplanken Fabrice,FRX ; Zunino Jean-Claude,FRX, Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device.

이 특허를 인용한 특허 (46)

  1. Guccione Steven A. ; Levi Delon, Configuration of programmable logic devices with routing core generators.
  2. Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Mohan Sundararajarao ; Wittig Ralph D., Context-sensitive self implementing modules.
  3. Akita,Koji; Ito,Hideki, DVD player and DVD playing method.
  4. Villarreal, Jason; Liu, Xiaoyong; Deepak, Kumar, Debugging system and method.
  5. Villarreal, Jason; Sankroj, Mahesh; Dhume, Nikhil A.; Deepak, Kumar, Debugging system and method.
  6. Glickman, Eran; Alankry, Yaron; Arbel-Meirovich, Erez; Parnes, Erez, Device and method for testing a circuit.
  7. Bryant, William K.; Freemon, Galen; Cornett, James W.; Fulton, Temple L.; Karklins, Gregory J., Devices, systems, and methods for configuring a programmable logic controller.
  8. Lewis, David; Betz, Vaughn, Error correction for programmable logic integrated circuits.
  9. Lewis,David; Betz,Vaughn, Error correction for programmable logic integrated circuits.
  10. Ngo, Ninh D.; Lee, Andy L.; Veenstra, Kerry, Error detection on programmable logic resources.
  11. Ngo, Ninh D.; Lee, Andy L.; Veenstra, Kerry, Error detection on programmable logic resources.
  12. Ngo,Ninh D.; Lee,Andy L.; Veenstra,Kerry, Error detection on programmable logic resources.
  13. Alfke Peter H., FPGA control structure for self-reconfiguration.
  14. Mohan Sundararajarao ; Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Wittig Ralph D., FPGA modules parameterized by expressions.
  15. Sun, Albert; Sheu, Eric; Lo, Ying-Che, Four state programmable interconnect device for bus line and I/O pad.
  16. L. James Hwang ; Eric F. Dellinger ; Sujoy Mitra ; Sundararajarao Mohan ; Cameron D. Patterson ; Ralph D. Wittig, Hetergeneous method for determining module placement in FPGAs.
  17. Hwang L. James ; Dellinger Eric F. ; Mitra Sujoy ; Mohan Sundararajarao ; Patterson Cameron D. ; Wittig Ralph D., Heterogeneous method for determining module placement in FPGAs.
  18. Guccione Steven A., Interactive dubug tool for programmable circuits.
  19. Mehr, Jamshid; Savin, Gregory Charles, Interface system for in-circuit emulator.
  20. Krzyzanowski, Paul; Lin, Wayzen, Legacy device bridge for residential or non-residential networks.
  21. Tobias David F., Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic.
  22. Dancea,Ioan, Method and VLSI circuits allowing to change dynamically the logical behavior.
  23. Delon Levi ; Steven A. Guccione, Method and apparatus for evolving a plurality of versions of a configuration bitstream in parallel.
  24. Delon Levi ; Steven A. Guccione, Method and apparatus for evolving configuration bitstreams.
  25. Levi, Delon; Guccione, Steven A., Method and apparatus for relocating elements in an evolvable configuration bitstream.
  26. Delon Levi ; Steven A. Guccione, Method and apparatus for remotely evolving configuration bitstreams.
  27. Delon Levi ; Steven A. Guccione, Method and apparatus for testing evolvable configuration bitstreams.
  28. Wollrath Ann M. ; Arnold Kenneth C. R. C., Method and apparatus for the suspension and continuation of remote processes.
  29. Patterson Cameron D. ; Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Mohan Sundararajarao ; Wittig Ralph D., Method for constraining circuit element positions in structured layouts.
  30. Horr, Olivier; Will, Patrick; Launay, Philippe, Method for downloading a configuration file in a programmable circuit, and apparatus comprising said component.
  31. L. James Hwang ; Cameron D. Patterson, Method for remapping logic modules to resources of a programmable gate array.
  32. Mohan Sundararajarao ; Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Wittig Ralph D., Method for specifying routing in a logic module by direct module communication.
  33. L. James Hwang ; Cameron D. Patterson ; Sujoy Mitra, Method for structured layout in a hardware description language.
  34. Chambers, II, Robert Baxter; Collier, David Scott; Mercer, Ferrell Louis; Kadingo, Jason Daniel; Newman, Robert Francis; Elliott, David Charles; Hietanen, David J., Methods and systems for management and control of an automation control module.
  35. Jacobson,Neil G., Network based diagnostic system and method for programmable hardware.
  36. Jacobson,Neil G., Network based diagnostic system and method for software reconfigurable systems.
  37. Debling, Anthony, On-chip emulator communication for debugging.
  38. Sun, Albert; Sheu, Eric; Lo, Ying-Che, One cell programmable switch using non-volatile cell.
  39. Sun, Albert; Sheu, Eric; Lo, Ying-Che, One cell programmable switch using non-volatile cell.
  40. Sun, Albert; Sheu, Eric; Lo, Ying-Che, One cell programmable switch using non-volatile cell with unidirectional and bidirectional states.
  41. Abdelilah, Youssef; Davis, Gordon Taylor; Derby, Jeffrey Haskell; Hwang, Dongming; Jeffries, Clark Debs; Ware, Malcolm Scott; Ye, Hua, Scoping of real time signals of remote communication systems over a computer network: systems, methods and program products.
  42. Draper, Andrew; Flaherty, Edward, Synchronization of hardware and software debuggers.
  43. Villarreal, Jason; Deepak, Kumar, System and method for debugging software executed as a hardware simulation.
  44. McGettigan,Edward S.; Fross,Bradley K.; Peattie,Michael E., Systems and methods of utilizing virtual input and output modules in a programmable logic device.
  45. Lewis, Shane, Virtual hardware system with universal ports using FPGA.
  46. Lauzon, David Martin; Lau, Christina P., Visual debugger for stylesheets.
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