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A intelligent power management apparatus for use with a matched-filter. A multiplexer multiplexes shifted-in-phase chips and shifted-quadrature-phase chips from an in-phase-shift register and a quadrature-phase-shift register, respectively, to generate multiplexed chips. The multiplexed chips includ

A intelligent power management apparatus for use with a matched-filter. A multiplexer multiplexes shifted-in-phase chips and shifted-quadrature-phase chips from an in-phase-shift register and a quadrature-phase-shift register, respectively, to generate multiplexed chips. The multiplexed chips include alternating sets of shifted-in-phase chips and shifted-quadrature-phase chips. A controller generates a POWERDOWN signal when the multiplexed chips from a received-spread-spectrum signal are unlikely to have a particular-chip sequence. The controller generates an ACTIVATION signal when the multiplexed chips are likely to have the particular-chip sequence present. An adder tree generates a CORRELATION signal when the multiplexed chips have the particular-chip sequence and match or correlate with the settings of the adder tree. A number of AND gates inhibit the multiplexed chips from passing to some or all of the adder tree when the POWERDOWN signal is present, and pass the multiplexed chips to some or all of the adder tree when the ACTIVATION signal is present.

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[ We claim:] [1.] An intelligent power management apparatus for a symbol-matched filter having a variable processing gain, comprising:an in-phase-shift register connected to a first input for shifting in-phase chips from said first input generated from a received-spread-spectrum signal as shifted-in

[ We claim:] [1.] An intelligent power management apparatus for a symbol-matched filter having a variable processing gain, comprising:an in-phase-shift register connected to a first input for shifting in-phase chips from said first input generated from a received-spread-spectrum signal as shifted-in-phase chips;a quadrature-phase-shift register connected to a second input for shifting quadrature-phase chips from said second input generated from the received-spread-spectrum signal as shifted-quadrature-phase chips;a multiplexer, coupled to said in-phase-shift register and to said quadrature-phase-shift register, for multiplexing the shifted-in-phase chips and the shifted-quadrature-phase chips from said in-phase-shift register and said quadrature-phase-shift register, respectively, thereby generating multiplexed chips, said multiplexed chips including alternating sets of shifted-in-phase chips and sets of shifted-quadrature-phase chips;a controller for generating an ACTIVATION signal at all times during an acquisition phase, said controller, responsive to a tracking signal from a tracking circuit indicating successful acquisition, for generating a POWERDOWN signal when the multiplexed chips are unlikely to have a particular-chip sequence, and for generating the ACTIVATION signal when the multiplexed chips are likely to have the particular-chip sequence;an adder tree having a plurality of adders for attempting to correlate the multiplexed chips with the particular-chip sequence, a subset of the plurality of adders being selectable responsive to application of the ACTIVATION signal to the subset, with a POWERDOWN signal being applied to a non-selected subset of the plurality of adders, whereby the processing gain of the symbol-matched filter may be varied dependent on the subset and the non-selected subset of the plurality of adders; anda plurality of AND gates coupled to said controller and between said multiplexer and said adder tree, responsive to the POWERDOWN signal, for inhibiting the multiplexed chips from passing to the non-selected subset of the plurality of adders, and responsive to the ACTIVATION signal, for passing the multiplexed chips to the subset of the plurality of adders selected.