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Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0954843 (1997-10-21)
발명자 / 주소
  • Willis John Christopher
  • Newshutz Robert Neill
출원인 / 주소
  • FTL Systems, Inc.
대리인 / 주소
    Lervick
인용정보 피인용 횟수 : 181  인용 특허 : 8

초록

A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The invention utilizes a hardware apparatus consisting of shared memory multiprocessors, optionally augment

대표청구항

[ What is claimed:] [1.] A parallel processor system with at least one node programmed to execute a distributed, compiler-oriented database, the parallel processor system including compilation, simulation and/or software execution operating modes, and comprising:at least two processors;memory operat

이 특허에 인용된 특허 (8)

  1. Ihara Sigeo (Tokorozawa JPX) Tanaka Teruo (Hachioji JPX) Iwasawa Kyoko (Tokyo JPX) Hamanaka Naoki (Tokyo JPX), Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer whic.
  2. Lazansky Richard W. (Pleasanton CA) Miller Thomas R. (Palo Alto CA) Coelho David R. (Fremont CA) Scott Kenneth E. (Fremont CA) Stanculescu Alec G. (San Mateo CA), Computer-aided engineering.
  3. Skillman Thomas L. (Bellevue WA) Blair Richard N. (Kent WA) Boland Arthur J. (Issaquah WA) Ling Yong-Long C. (Bellevue WA) Pier Richard M. (Bellevue WA), Event driven blackboard processing system that provides dynamic load balancing and shared data between knowledge source.
  4. Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
  5. Sample Stephen P. ; Bershteyn Mikhail, Method and apparatus for design verification using emulation and simulation.
  6. Hunt Peter D. (Pleasanton CA) Elliott Jon K. (Pleasanton CA) Tobias Richard J. (San Jose CA) Herring Alan J. (San Jose CA) Morgan Craig R. (San Jose CA) Hiller John A. (Palo Alto CA), Method for automated deployment of a software program onto a multi-processor architecture.
  7. Tanaka Teruo (Hachioji JPX) Inagami Yasuhiro (Kodaira JPX) Tamaki Yoshiko (Kodaira JPX) Sakakibara Tadayuki (Kunitachi JPX) Kitai Katsuyoshi (Hadano JPX), Parallel processing system and compiling method used therefor.
  8. Rupp Charle R., Reconfigurable computer architecture for use in signal processing applications.

이 특허를 인용한 특허 (181)

  1. Willis, John Christopher, Accelerating simulation of differential equation systems having continuous behavior.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  11. Blocksome, Michael A.; Miller, Douglas R., Administering an epoch initiated for remote memory access.
  12. Blocksome, Michael A.; Miller, Douglas R., Administering an epoch initiated for remote memory access.
  13. Faraj, Daniel A.; Smith, Brian E., Administering connection identifiers for collective operations in a parallel computer.
  14. Faraj, Daniel A.; Smith, Brian E., Administering connection identifiers for collective operations in a parallel computer.
  15. Faraj, Daniel A.; Smith, Brian E., Administering connection identifiers for collective operations in a parallel computer.
  16. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  17. Cook,Stephen; Broadley,Simon; Bilton,Mark; Farr,Mark; Wimpory,Ben; Hewitt,Lee; Glover,Tim, Apparatus and method for managing integrated circuit designs.
  18. Wheeler,William R.; Hui,Lai Wah; Hooper,Donald F.; Kornfeld,Serge; Guilford,James D., Apparatus and method of developing software for a multi-processor chip.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  20. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  21. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  22. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  23. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  24. Earl A. Killian ; Ricardo E. Gonzalez ; Ashish B. Dixit ; Monica Lam ; Walter D. Lichtenstein ; Christopher Rowen ; John C. Ruttenberg ; Robert P. Wilson ; Albert Ren-Rui Wang ; Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
  25. Killian, Earl A.; Gonzalez, Ricardo E.; Dixit, Ashish B.; Lam, Monica; Lichtenstein, Walter D.; Rowen, Christopher; Ruttenberg, John C.; Wilson, Robert P.; Wang, Albert Ren-Rui; Maydan, Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
  26. Killian, Earl A.; Gonzalez, Ricardo E.; Dixit, Ashish B.; Lam, Monica; Lichtenstein, Walter D.; Rowen, Christopher; Ruttenberg, John C.; Wilson, Robert P.; Wang, Albert Ren-Rui; Maydan, D{grave over , Automated processor generation system for designing a configurable processor and method for the same.
  27. Killian,Earl A.; Gonzalez,Ricardo E.; Dixit,Ashish B.; Lam,Monica; Lichtenstein,Walter D.; Rowen,Christopher; Ruttenberg,John C.; Wilson,Robert P.; Wang,Albert Ren Rui; Maydan,Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
  28. Sturrock, David Thayer; Drake, Glenn Richardson; Crooks, Cory R; Takus, A David; Glavach, Mark Anson; O'Neill Kolt, Genevieve; Palmieri, Jr., Frank Anthony, Automated recommendations from simulation.
  29. Abu el Ata, Nabil A.; Desmichels, Marc; Drucbert, Annie; Spelman, Guy; Blunt, Jonathan, Automated system and method for service and cost architecture modeling of enterprise systems.
  30. Kulkarni, Pradip; Kumar, Mukul; Potdar, Adhir; Au, Richard; Mott, James M.; Nguyen, Tung M., Block-level I/O subsystem for distributed application environment management.
  31. Steiner, Steven J., Building call tree branches and utilizing break points.
  32. Niederer, Theron Paul; Singh, Raj Kumar; Trombley, Michael Raymond, Client/server behavioral modeling and testcase development using VHDL for improved logic verification.
  33. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  34. Wallach, Steven J.; Brewer, Tony, Compiler for generating an executable comprising instructions for a plurality of different instruction sets.
  35. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  36. Gonzalez, Ricardo E.; Rudell, Richard L.; Ghosh, Abhijit; Wang, Albert R., Configuring a multi-processor system.
  37. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  38. Winberg, Mats; Winberg, Lars; Linnermark, Nils Ola; Hemetek, Marijan, Data value coherence in computer systems.
  39. Hammarlund, Per H.; Jourdan, Stephan J.; Michaud, Pierre; Farcy, Alexandre J.; Marden, Morris; Hinton, Robert L.; Carmean, Douglas M., Decoupling the number of logical threads from the number of simultaneous physical threads in a processor.
  40. Williams,Kenneth M; Wang,Albert, Defining instruction extensions in a standard programming language.
  41. Griffin, Jed D., Differential amplifier output stage.
  42. Wallach, Steven J.; Brewer, Tony, Dispatch mechanism for dispatching instructions from a host processor to a co-processor.
  43. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Distributed administration of a lock for an operational group of compute nodes in a hierarchical tree structured network.
  44. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Distributed hardware device simulation.
  45. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Distributed hardware device simulation.
  46. Shakeri, Mojdeh; Mosterman, Pieter J., Distributed model compilation.
  47. Wasynczuk,Oleg; Lucas,Charles E.; Walters,Eric A.; Jatskevich,Juri V., Distributed simulation.
  48. Sturrock, David Thayer; Drake, Glenn Richardson; Crooks, Cory R.; Takus, A. David; Glavach, Mark Anson; Kolt, Genevieve O'Neill; Palmieri, Jr., Frank Anthony, Distributed simulation and synchronization.
  49. Brewer, Tony; Wallach, Steven J., Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor.
  50. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E.; Xue, Hanhong, Establishing a group of endpoints in a parallel computer.
  51. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E.; Xue, Hanghong, Establishing a group of endpoints to support collective operations without specifying unique identifiers for any endpoints.
  52. Parthasarathy,Sivagnanam; Cofler,Andrew; Chaverot,Lionel, Executing cache instructions in an increased latency mode.
  53. Johnson, Scott D., Extension adapter.
  54. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  55. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  56. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  57. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  58. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Sidelnik, Albert; Smith, Brian E., Generating an executable version of an application using a distributed compiler operating on a plurality of compute nodes.
  59. Sinha, Navendu; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Attias, Roberto; Deshpande, Akash Renukadas; Gupta, Vineet; Sonakiya, Shobhit, Generating hardware accelerators and processor offloads.
  60. Garvey,Joseph F.; Jeffries,Clark D., Global processor resource assignment in an assembler.
  61. Sinha, Navendu; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Attias, Roberto; Deshpande, Akash Renukadas; Gupta, Vineet; Sonakiya, Shobhit, Hardware accelerator test harness generation.
  62. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  63. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  64. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  65. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  66. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  67. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Identifying data communications algorithms of all other tasks in a single collective operation in a distributed processing system.
  68. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Identifying data communications algorithms of all other tasks in a single collective operation in a distributed processing system.
  69. Williams,Kenneth Mark; Johnson,Scott Daniel; McNamara,Bruce Saylors; Wang,Albert RenRui, Instruction set for efficient bit stream and byte stream I/O.
  70. Guhr, Jerry T.; Picone, Joseph, Integrated development environment for high speed transaction processing WWW applications on heterogeneous computer systems.
  71. Spertus, Michael P.; Fiterman, Charles; Rodriguez Rivera, Gustavo, Interactive debugging system with debug data base system.
  72. Spertus, Michael P.; Fiterman, Charles; Rodriguez Rivera, Gustavo, Interactive debugging system with debug data base system.
  73. Oshima, Yoshiki; Tanimoto, Tadaaki, Language conversion method and language conversion program.
  74. Acher, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Locality mapping in a distributed processing system.
  75. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Locality mapping in a distributed processing system.
  76. Gonzalez,Ricardo E.; Johnson,Scott; Taylor,Derek, Long instruction word processing with instruction extensions.
  77. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  78. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  79. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  80. Sanders, David, Medical injector.
  81. Latta, David, Memory interface and method of interfacing between functional entities.
  82. Latta, David, Memory interface and method of interfacing between functional entities.
  83. Latta, David, Memory interface and method of interfacing between functional entities.
  84. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.
  85. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.
  86. Abu El Ata Nabil A., Method and apparatus for designing and analyzing information systems using multi-layer mathematical models.
  87. Abu El Ata, Nabil A., Method and apparatus for designing and analyzing information systems using multi-layer mathematical models.
  88. Self, Keith; Urbanski, John, Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect.
  89. Kumar,Anoop; Nair,Sreekumar Ramakrishnan, Method and apparatus for integrated instruction scheduling and register allocation in a postoptimizer.
  90. Khare, Manoj; Kumar, Akhilesh; Creta, Ken; Looi, Lily P.; George, Robert T.; Cekleov, Michel, Method and apparatus for invalidating a cache line without data return in a multi-node architecture.
  91. Hakewill,James Robert Howard; Sanders,John, Method and apparatus for jump control in a pipelined processor.
  92. P. Krishnan ; Danny Raz ; Yuval Shavitt, Method and apparatus for locating caches in a network to optimize performance.
  93. Hakewill, James Robert Howard; Khan, Mohammed Noshad; Plowman, Edward, Method and apparatus for managing the configuration and functionality of a semiconductor design.
  94. Hakewill, James Robert Howard; Khan, Mohammed Noshad; Plowman, Edward, Method and apparatus for managing the configuration and functionality of a semiconductor design.
  95. Khare, Manoj; Kumar, Akhilesh; Schoinas, Ioannis; Looi, Lily Pao, Method and apparatus for managing transaction requests in a multi-node architecture.
  96. Lu, Jiwei Oliver; Yamada, Koichi; Beany, James D.; Shanmugavelayutham, Palaniverlrajan; Zhang, Bo, Method and apparatus for page-level monitoring.
  97. Khare, Manoj; Kumar, Akhilesh; Tan, Sin Sim, Method and apparatus for preventing starvation in a multi-node architecture.
  98. Manoj Khare ; Akhilesh Kumar, Method and apparatus for preventing starvation in a multi-node architecture.
  99. Khare,Manoj; Briggs,Faye A.; Kumar,Akhilesh; Looi,Lily P.; Cheng,Kai, Method and apparatus for reducing memory latency in a cache coherent multi-node architecture.
  100. Williams, Mark, Method and apparatus to make and transmit objects from a database on a server computer to a client computer.
  101. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  102. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  103. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  104. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  105. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  106. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  107. Aubertine,Matthew Edward, Method and system for optimizing the use of processors when compiling a program.
  108. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  109. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  110. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  111. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  112. Maxwell, III, Sidney Richards; Steinberger, Michael Louis, Method and system for simulating execution of a target program in a simulated target system.
  113. Harcourt,Edwin A.; Roy,Koushik; Dunlop,Doug; Rae,Stuart C.; Lang,Tuay Ling K.; Wilmot,Andrew; Bhattacharya,Bishnupriya; Shur,Robert, Method and system for simulation of mixed-language circuit designs.
  114. Grover, Vinod; Kerr, Andrew; Lee, Sean, Method for compiling a parallel thread execution program for general execution.
  115. Hunter, Jeff L.; Buser, Mark L.; Lee, Bruce W.C.; Ali, Imtaz, Method for maintaining cache coherency in software in a shared memory system.
  116. O'Brien, John Kevin Patrick; O'Brien, Kathryn M.; Prener, Daniel A., Method for partitioning programs between a general purpose core and one or more accelerators.
  117. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  118. Ebeling, W. H. Carl; Hogenauer, Eugene B., Method, system and software for programming reconfigurable hardware.
  119. Kim, James Sangkyu; Sun, Fei; Tsukamoto, Kyle Satoshi, Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network.
  120. Paul Gerard D'Arcy ; Pamela C. Deschler ; Sanjay Jinturkar ; Kamesh Peri ; Ramesh V. Peri ; David B. Whalley, Methods and apparatus for simulating external linkage points and control transfers in source translation systems.
  121. Rajaraman, Prasanna, Methods and systems for optimizing the performance of software applications at runtime.
  122. Wallach, Steven J.; Brewer, Tony, Microprocessor architecture having alternative memory access paths.
  123. Kruglick, Ezekiel; Fine, Kevin S., Migration of executing processes.
  124. Miller, Douglas R., Minimally buffered data transfers between nodes in a data communications network.
  125. Michelle R. Akin, Modified design representation for fast fault simulation of an integrated circuit.
  126. Wallach, Steven J.; Brewer, Tony, Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set.
  127. Askins, Timothy M.; MacCracken, Ronald A.; Fox, Randy J.; Ohlund, Kent O. I., Multi-threaded frame safe synchronization of a simulation.
  128. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  129. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  130. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  131. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  132. Deao, Douglas; Keil, Deborah; McGowan, Robert; McLean, Craig; Swoboda, Gary; Szewerenko, Leland, Multiprocessor emulation support using dynamic linking.
  133. Liao, Heng, Multithreaded address resolution system.
  134. Terence Chan, Multithreaded, mixed hardware description languages logic simulation on engineering workstations.
  135. O'Brien, John Kevin Patrick; O'Brien, Kathryn M.; Prener, Daniel A., Partitioning programs between a general purpose core and one or more accelerators.
  136. Liu, Xuezheng; Lin, Wei; Zhang, Zheng, Predicate checking for distributed systems.
  137. Cumplido,Rene; Goodall,Roger; Jones,Simon, Processor apparatus and methods optimized for control applications.
  138. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  139. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Programmable logic configuration for instruction extensions.
  140. Christensen Brent Ray ; Davis Howard Rollin ; Harral Adam Lee, Proxy cache cluster.
  141. Daudel, Jeffrey; Jakab, Arpad; Cherukuri, Suman; Lindo, Johnathan, Recording and replaying computer program execution with log amplification logic.
  142. Daudel, Jeffrey; Jakab, Arpad; Cherukuri, Suman; Lindo, Jonathan, Recording and replaying computer program execution with recorded execution event breakpoints.
  143. Kulkarni, Pradip; Kumar, Mukul; Potdar, Adhir; Au, Richard; Nguyen, Tung, Root image caching and indexing for block-level distributed application management.
  144. Faraj, Daniel A.; Smith, Brian E., Runtime optimization of an application executing on a parallel computer.
  145. Faraj, Daniel A.; Smith, Brian E., Runtime optimization of an application executing on a parallel computer.
  146. Faraj, Daniel A.; Smith, Brian E., Runtime optimization of an application executing on a parallel computer.
  147. Willis,John Christopher, Semi-automatic generation of behavior models continuous value using iterative probing of a device or existing component model.
  148. Barsness, Eric L.; Darrington, David L.; Peters, Amanda; Santosuosso, John Matthew, Sharing compiler optimizations in a multi-node system.
  149. Barsness, Eric L.; Darrington, David L.; Peters, Amanda; Santosuosso, John Matthew, Sharing compiler optimizations in a multi-node system.
  150. Sturrock, David T.; Morse, Richard A., Simulation controls for model variablity and randomness.
  151. Askins, Timothy M.; MacCracken, Ronald A., Simulation program having generic attribute access schema.
  152. Master,Paul L.; Watson,John, Storage and delivery of device features.
  153. Nesbitt,Richard Elderkin; O'Connell,Brian Marshall; Vaughan,Kevin Edward, System and method for grid-based distribution of Java project compilation.
  154. Abu El Ata,Nabil A., System and method for improving predictive modeling of an information system.
  155. Abu El Ata,Nabil A.; Zelechoski,Peter M., System and method for multi-phase system development with predictive modeling.
  156. Major, Robert Drew; Carter, Stephen R; Davis, Howard Rollin; Christensen, Brent Ray, System and method for partitioning address space in a proxy cache server cluster.
  157. Craig Chambers ; Susan J. Eggers ; Brian K. Grant ; Markus Mock ; Matthai Philipose, System and method for performing selective dynamic compilation using run-time information.
  158. Cormac A. Flanagan ; Andrew B. Bernard, System and method for statically detecting potential race conditions in multi-threaded computer programs.
  159. Orman,Hilarie; Davis,Howard Rollin; Mahdavi,Jamshid, System and method for transparent takeover of TCP connections between servers.
  160. Killian, Earl A.; Gonzalez, Ricardo E.; Dixit, Ashish B.; Lam, Monica; Lichtenstein, Walter D.; Rowen, Christopher; Ruttenberg, John C.; Wilson, Robert P.; Wang, Albert Ren-Rui; Maydan, Dror Eliezer, System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions.
  161. Killian, Earl A.; Gonzalez, Ricardo E.; Dixit, Ashish B.; Lam, Monica; Lichtenstein, Walter D.; Rowen, Christopher; Ruttenberg, John C.; Wilson, Robert P.; Wang, Albert Ren-Rui; Maydan, Dror Eliezer, System and method of designing instruction extensions to supplement an existing processor instruction set architecture.
  162. Abu El Ata,Nabil A.; Drucbert,Annie; Abu El Ata,Ahmad, System and method of predictive modeling for managing decisions for business enterprises.
  163. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  164. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  165. Abu El Ata, Nabil A.; Drucbert, Annie, Systemic enterprise management method and apparatus.
  166. Abu El Ata,Nabil A., Systems and method for determining performance metrics for constructing information systems.
  167. Wang, Qinghua; Watts, III, James William, Systems and methods for improved parallel ILU factorization in distributed sparse linear systems.
  168. Qin, Yinghua; Fahimi Chahestani, Hassan; Song, Zhenlei, Systems and methods for integrated modeling and performance measurements of monitored virtual desktop infrastructure systems.
  169. Qin, Yinghua; Song, Zhenlei; Ji, Zhong Hong, Systems and methods for integrated modeling of monitored virtual desktop infrastructure systems.
  170. Brewer, Tony, Systems and methods for mapping a neighborhood of data to general registers of a processing element.
  171. Chen, Yuling; Qin, Yinghua, Systems and methods for multilayer monitoring of network function virtualization architectures.
  172. Pan, Lei; Bic, Lubomir R.; Dillencourt, Michael B., Systems and methods for parallel distributed programming.
  173. Gonzalez, Ricardo E.; Wang, Albert R., Systems and methods for selecting input/output configuration in an integrated circuit.
  174. Gonzalez, Ricardo E.; Wang, Albert R.; Banta, Gareld Howard, Systems and methods for software extensible multi-processing.
  175. Sager, David J.; Sasanka, Ruchira; Gabor, Ron; Raikin, Shlomo; Nuzman, Joseph; Peled, Leeor; Domer, Jason A.; Kim, Ho-Seop; Wu, Youfeng; Yamada, Koichi; Ngai, Tin-Fook; Chen, Howard H.; Bobba, Jayaram; Cook, Jeffery J.; Shaikh, Omar M.; Srinivas, Suresh, Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads.
  176. Sasanka, Ruchira; Das, Abhinav; Cook, Jeffrey J.; Bobba, Jayaram; Krishnaswamy, Arvind; Sager, David J.; Srinivas, Suresh, Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads.
  177. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  178. Rupp,Charle' R., Transitive processing unit for performing complex operations.
  179. Bobba, Jayaram; Sasanka, Ruchira; Cook, Jeffrey J.; Das, Abhinav; Krishnaswamy, Arvind; Sager, David J.; Agron, Jason M., Using control flow data structures to direct and track instruction execution.
  180. Fakhry, Nader; Lakshmanan, Viswanathan, Verilog to vital translator.
  181. Arnold,Jeffrey Mark; Banta,Gareld Howard; Johnson,Scott Daniel; Wang,Albert R., Video processing system with reconfigurable instructions.
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