초록

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("G

대표청구항 ▼

[ What is claimed is:] [1.] A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) bus and a peripheral component interconnect (PCI) bus, said system comprising:a system processor executing software instructions and generati

[ What is claimed is:] [1.] A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) bus and a peripheral component interconnect (PCI) bus, said system comprising:a system processor executing software instructions and generating graphics data;a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage;an accelerated graphics port (AGP) processor connected to an AGP bus and generating video display data from the graphics data and adapted for a video display to display the video display data;a core logic chipset having a first interface logic for connecting said system processor to said system memory;said core logic chipset having a second interface logic for connecting said system processor and said system memory to input-output devices on a peripheral component interconnect (PCI) bus;said core logic chipset having a third interface logic for connecting said system processor and said system memory to said AGP bus;said core logic chipset having a fourth interface logic for connecting said AGP bus to said PCI bus;said second interface logic having a base address register;said fourth interface logic having an AGP device address space size register;said AGP device address space size register having a value which indicates the size of an AGP device address space required by said AGP processor; andsaid fourth interface logic communicating the value in said AGP device address space size register to said second interface logic so that a corresponding value is stored in said base address register, wherein the corresponding value stored in said base address register is used by computer system memory mapping software to configure the size of the AGP device address space, the AGP device address space being within the addressable memory space, and said base address register storing a base address value of the AGP device address space after the size of the AGP device address space is configured.