[특허]Damage free passivation layer etching process

Damage free passivation layer etching process 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G03F-007/40 G03F-007/36 B44C-001/22 C03L-015/00 C23F-001/00
출원번호	US-0055442 (1998-04-06)
발명자 / 주소	Chen Sen-Fu,TWX Wu Jie-Shing,TWX Chen Fang-Cheng,TWX Lee Tsung-Tser,TWX
출원인 / 주소	Taiwan Semiconductor Manufacturing Company Ltd., TWX
대리인 / 주소	Saile
인용정보	피인용 횟수 : 47 인용 특허 : 4

초록 ▼

A method for etching bonding pad access openings in a passivation layer of an integrated circuit is described. The method utilizes a two step etching procedure wherein the first step etches isotropically through a major portion of the passivation layer under conditions which provide very high etch rate selectivities of the passivation material to the photoresist. These high selectivitities result in virtually no erosion of the photoresist while the greater part of the opening is etched. A second anisotropic etch step wherein the base of the access opening is defined faithfully replicates the dimensions of the mask pattern. This two step etch process permits the use of photoresist layers of moderate thickness as well as photoresist layers with thin regions, such as occur when the photoresist is deposited over the uneven surface topography typically found on unplanarized passivation layers. The minimal erosion of the photoresist during the isotropic etch step secures sufficient photoresist coverage in the thin regions to prevent penetration and attack of passivation over wiring lines in the uppermost wiring level of the integrated circuit.

대표청구항 ▼

[ What is claimed is:] [1.] A method for etching an insulative layer to provide an opening to a metal pad:(a) providing a silicon wafer having a metal pad over which has been deposited a composite layer comprising a first insulative layer and a second insulative layer on said first insulative layer;(b) depositing a masking layer over said silicon wafer;(c) patterning said masking layer to define an access opening to said metal pad;(d) isotropically etching said second insulative layer and a first portion of said first insulative layer in a plasma containing a first gas mixture; and(e) anisotropically etching a remaining portion of said first insulative layer in plasma containing a second gas mixture thereby exposing said metal pad.

이 특허에 인용된 특허 (4)

Carmody Kevin F. (Hillsboro OR) Charvat Peter K. (Portland OR) Vandentop Gilroy J. (Aloha OR), Method for etching silicon oxide films in a reactive ion etch system to prevent gate oxide damage.
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Grewal Virinder (Ebersberg DEX), Method for generating contact holes with beveled sidewalls in intermediate oxide layers.
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Shan Hongging (San Jose CA) Jillie ; Jr. Donald W. (Cupertino CA), Process for etching silicon dioxide layer without micro masking effect.
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Meyer Theodore O. (Bend OR), Profile tailored trench etch using a SF₆-O₂ etching composition wherein both isotropic and a.
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이 특허를 인용한 특허 (47)

Lau, Wesley George, Cleaning process residues from substrate processing chamber components.
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Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Coaxial integrated circuitry interconnect lines, and integrated circuitry.
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Ahn Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
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Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
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Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
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Kim,Jisoo; Lee,Sangheon; Worsham,Binet A.; Charatan,Robert; Sadjadi,S.M. Reza, Etch with photoresist mask.
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Jiahua Huang ; Jeffrey A. Shields ; Allison Holbrook, High selectivity pad etch for thick topside stacks.
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Ahn Kie Y., Integrated circuitry and methods of forming integrated circuitry.
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Kie Y. Ahn, Integrated circuitry having conductive passageway interconnecting circuitry on front and back surfaces of a wafer fragment.
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Yeoh, Terence Sern-Wei; Ives, Neil A., Isosurfacial three-dimensional imaging system and method.
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Hong,Liubo; Zhong,Tom; Yang,Lin, MRAM cell structure and method of fabrication.
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Yauw, Oranna; Shen, Meihua; Gani, Nicolas; Chinn, Jeffrey D., Method of etching organic antireflection coating (ARC) layers.
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Chia-Mei Huang TW; Chao-Yi Lan TW; Hsiao-Ping Chang TW; Chia-Kung Chang TW, Method of protecting a bond pad structure, of a color image sensor cell, during a color filter fabrication process.
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Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Methods of forming coaxial integrated circuitry interconnect lines.
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Kanda,Atsushi, Pad structures including insulating layers having a tapered surface.
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Shimomura, Koji; Kinoshita, Yoshiaki; Funato, Satoru; Yamaguchi, Yuko, Pattern forming method.
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Fuse,Takashi, Plasma processing method.
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Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
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Kanda, Atsushi, Semiconductor devices and methods of fabricating the same.
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Chen, Hsien-Wei; Yeh, Der-Chyang; Huang, Li-Hsien, Stacked semiconductor devices and methods of forming same.
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Sung, Fu-Ting; Hsu, Chern-Yow; Liu, Shih-Chang, Storage device with composite spacer and method for manufacturing the same.
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Yang Chih Yuh ; Lyons Christopher F. ; Levinson Harry J. ; Nguyen Khanh B. ; Wang Fei ; Bell Scott A., Thin resist with amorphous silicon hard mask for via etch application.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
상세보기

Lin,Mou Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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Wang, Xikun; Williams, Scott; Pan, Shaoher X., Two-stage etching process.
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Wang Fei ; Lyons Christopher F. ; Nguyen Khanh B. ; Bell Scott A. ; Levinson Harry J. ; Yang Chih Yuh, Ultra-thin resist and SiON/oxide hard mask for metal etch.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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연합인증

Damage free passivation layer etching process 원문보기

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이 특허를 인용한 특허 (47)

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Damage free passivation layer etching process 원문보기

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이 특허에 인용된 특허 (4)

이 특허를 인용한 특허 (47)

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