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Ball grid array (BGA) encapsulation mold 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B29C-045/02
  • B29C-045/14
출원번호 US-0034499 (1998-03-04)
발명자 / 주소
  • Mess Leonard E.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Trask, Britt & Rossa
인용정보 피인용 횟수 : 24  인용 특허 : 28

초록

A molding machine for encapsulating electronic devices mounted on one side of a substrate, and having a ball-grid array, pin-grid array, or land-grid array on the opposite side, has a two member biased floating plate apparatus to compensate for variations in substrate thickness, and a gas collection

대표청구항

[ What is claimed is:] [1.] A molding machine for plastic-encapsulating an electronic device mounted on a first side of a planar substrate, comprising:mating upper and lower mold plates having cavities therein for enclosing said device and a portion of said substrate;clamping apparatus on said upper

이 특허에 인용된 특허 (28)

  1. Bhattacharyya Bidyut K. (Chandler AZ) Mallik Debendra (Chandler AZ) Ban Syunsuke (Hyogo JPX) Takikawa Takatoshi (Hyogo JPX) Yamanaka Shosaku (Hyogo JPX), Advance multilayer molded plastic package using mesic technology.
  2. Weber Patrick O. (San Jose CA), Apparatus for encapsulating electronic packages.
  3. De\Ath Roderick M. (Oxfordshire GB2), Apparatus for injection moulding.
  4. Saito Hiroshi (Hamamatsu JPX), Ball grid array type semiconductor device.
  5. Marrs Robert C. (Scottsdale AZ) Hirakawa Tadashi (Osaka JPX), Ball grid array with via interconnection.
  6. Golwalkar Suresh V. (Folsom CA) Foehringer Richard (Fair Oaks CA) Wentling Michael (Cameron Park CA) Takatsuki Ryo (Ibaraki-ken JPX) Kawashima Shigeo (Kitakyusyu JPX) Tsujimoto Keiichi (Kitakyusyu JP, Dual sided integrated circuit chip package with offset wire bonds and support block cavities.
  7. Neu H. Karl (Furlong PA), Encapsulaton molding equipment.
  8. DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA) Faraci Tony (Georgetown TX), Fan-out semiconductor chip assembly.
  9. Schmid Hermann (Schwaig DEX), Injection mold for producing the housings of integrated circuits.
  10. , Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding.
  11. Variot Patrick (San Jose CA), Method for encapsulating an integrated circuit package.
  12. Leveque Denis J. (Milwaukee WI) Czarnecki Neil A. (Mukwonago WI), Method for forming a molded plastic article.
  13. McShane Michael B. (Austin TX) Casto James J. (Austin TX) Joiner Bennett A. (Austin TX), Method for making a thermally enhanced semiconductor device by holding a leadframe against a heatsink through vacuum suc.
  14. Djennas Frank (Austin TX) Nomi Victor K. (Round Rock TX) Pastore John R. (Leander TX) Reeves Twila J. (Austin TX) Postlethwait Les (Lexington TX), Method for making semiconductor device having no die supporting surface.
  15. Drummond Brian (Austin TX), Method for molding using venting pin.
  16. Karavakis Konstantine (Coram NY) Distefano Thomas H. (Monte Sereno CA) Smith ; Jr. John W. (Austin TX) Mitchell Craig (San Jose CA), Method of encapsulating die and chip carrier.
  17. Sweis Jason (Sunnyvale CA) Gilleo Kenneth B. (West Kingston RI), Method of forming interface between die and chip carrier.
  18. Newman Keith G. (Sunnyvale CA), Method of making integrated circuit package having multiple bonding tiers.
  19. Oyama Kenshu (Ogouri JPX), Method of manufacturing an electronics package.
  20. Hosokawa Ryuji (Yokohama JPX) Yanagida Satoru (Kawasaki JPX), Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semi.
  21. Woosley Alan H. (Austin TX) Downey ; Jr. Harold A. (Austin TX) Mace Everitt W. (Hutto TX), Method of packaging a semiconductor device.
  22. Peters Gerardus Franciscus Wilhelmus,NLX ; Peters Hendrikus Johannus Beernardus,NLX, Moulding apparatus with compensation element.
  23. Wakefield Gene F. (Plano TX), Plastic package with solder grid array.
  24. Heckman James K. (Tempe AZ) Carney Francis J. (Gilbert AZ) Geyer Harry J. (Phoenix AZ), Semiconductor chip package and method of forming.
  25. Hatakeyama Atsushi (Kawasaki JPX) Baba Fumio (Kawasaki JPX) Kasai Junichi (Kawasaki JPX) Sato Mitsutaka (Kawasaki JPX), Semiconductor device having a plurality of chips having identical circuit arrangement sealed in package.
  26. Waki Masaki (Kagoshima JPX) Honda Tosiyuki (Kawasaki JPX) Gomi Yukio (Kawasaki JPX), Semiconductor device having a plurality of semiconductor chips.
  27. Haley Kevin (San Jose CA), Tape BGA package die-up/die down.
  28. Ishii Masaaki (Fukuoka JPX), Transfer molding machine for encapsulation of semiconductor devices.

이 특허를 인용한 특허 (24)

  1. Thummel, Steven G., Apparatus for encasing array packages.
  2. Thummel, Steven G., Apparatus for encasing array packages.
  3. Chua Kok Hua,SGX ; Fang Ching Meng,SGX ; Tan Kim Hwee,SGX, Encapsulated circuit using vented mold.
  4. Mess, Leonard E., Encapsulation method in a molding machine for an electronic device.
  5. Tandy, Patrick W., Encapsulation mold with a castellated inner surface.
  6. Thummel Steven G., Method for encasing array packages.
  7. Thummel, Steven G., Method for encasing array packages.
  8. Thummel,Steven G., Method for encasing plastic array packages.
  9. Singh, Harvinder, Method for making a circuit assembly having an integral frame.
  10. Nair, Vijay K.; Meyer, Thorsten, Method of embedding WLCSP components in E-WLB and E-PLB.
  11. Nair, Vijay K.; Meyer, Thorsten, Method of embedding WLCSP components in e-WLB and e-PLB.
  12. Murugan, Selvarajan; Rafaie, Abdul Rahman Mohamed, Methods and apparatus to evenly clamp semiconductor substrates.
  13. Tandy,Patrick W., Mold assembly for a package stack via bottom-leaded plastic (BLP) packaging.
  14. Tandy, Patrick W., Mold assembly for a package stack via bottom-leaded plastic (blp) packaging.
  15. Tandy Patrick W., Package stack via bottom leaded plastic (BLP) packaging.
  16. Tandy Patrick W., Package stack via bottom leaded plastic (BLP) packaging.
  17. Tandy Patrick W., Package stack via bottom leaded plastic (BLP) packaging.
  18. Tandy Patrick W., Package stack via bottom leaded plastic (BLP) packaging.
  19. Tandy Patrick W., Package stack via bottom leaded plastic (BLP) packaging.
  20. Luettgen, Michael John; Degrood, Susan Marie, Protected electronic assembly.
  21. Chien-ping Huang TW; Cheng-Yuan Lai TW; Tzu-Yi Tien TW; Chih-Ming Huang TW, Semiconductor package with a heat sink.
  22. Farnworth Warren M. ; Hembree David R. ; Gochnour Derek ; Akram Salman ; Jacobson John O. ; Wark James M. ; Thummel Steven G., Semiconductor package with pre-fabricated cover.
  23. Mistry, Addi B.; Mangrum, Marc A.; Patten, David T.; Phou, Jesse; Tran, Ziep, Stackable molded packages and methods of making the same.
  24. Gao, Zheng Yu; Ho, Shu Chuen, Vacuum molding apparatus.
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