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Flexible contact post and post socket and associated methods therefor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-009/09
출원번호 US-0775945 (1997-01-03)
발명자 / 주소
  • Distefano Thomas H.
  • Fjelstad Joseph
출원인 / 주소
  • Tessera, Inc.
대리인 / 주소
    Lerner, David, Littenberg, Krumholz & Mentlik, LLP
인용정보 피인용 횟수 : 79  인용 특허 : 14

초록

Flexible connectors having substantially vertical conductive legs allowing the connectors to accommodate deflection in the lateral directions (x-y directions in the plane of the connectors) induced by CTE mismatches between a chip and a substrate during thermal cycling of the chip. The connectors al

대표청구항

[ What is claimed is:] [1.] A flexible connector for interconnecting microelectronic devices, comprising:a plurality of conductive legs each having a first end and a second end;a top connected to the first end of each leg;a base conductively interconnecting the second end of each leg together, where

이 특허에 인용된 특허 (14)

  1. Frey Brenda D. (Binghamton NY) Joseph Charles A. (Candor NY) Olshefski Francis J. (Endicott NY) Wilson James W. (Vestal NY), Chip carrier with protective coating for circuitized surface.
  2. Scholz Kenneth D. (4150 Willmar Dr. Palo Alto CA 94306), Compressive bump-and-socket interconnection scheme for integrated circuits.
  3. Patraw Nils E. (Redondo Beach CA), Compressive pedestal for microminiature connections.
  4. Patraw Nils E. (Redondo Beach CA), Compressive pedestal for microminiature connections.
  5. Papathomas Kostas (Endicott) Poliks Mark D. (Vestal) Wang David W. (Vestal) Christie Frederick R. (Endicott NY), Dielectric composition and solder interconnection structure for its use.
  6. Difrancesco Louis (Hayward CA), Electrical interconnect using particle enhanced joining of metal surfaces.
  7. Jacobs Scott L. (Apex NC), Extended integration semiconductor structure with wiring layers.
  8. Chapin Fletcher W. (Vestal NY) Dranchak David W. (Endwell NY) Engle David E. (Vestal NY) Hall Richard R. (Endwell NY) Macek Thomas G. (Endicott NY), High density connector.
  9. Karnezos Marcos (Palo Alto CA), Interconnect structure for PC boards and integrated circuits.
  10. Jacobs Scott L. (Apex NC), Method of making a extended integration semiconductor structure.
  11. Nelson Gregory H. (Gilbert AZ), Method of manufacturing an interconnect device having coplanar contact bumps.
  12. Schreiber Christopher M. (Newport Beach CA) Crumly William R. (Anaheim CA), Resilient interconnection bridge.
  13. Walker George F. (New York NY) Zingher Arthur (White Plains NY), Spring array connector.
  14. Banerji Kingshuk (Plantation) Alves Francisco D. (Boca Raton) Darveaux Robert F. (Coral Springs FL), Vacuum infiltration of underfill material for flip-chip devices.

이 특허를 인용한 특허 (79)

  1. Momenpour, Saeed; Brunelle, Steven J., Adapter for non-permanently connecting integrated circuit devices to multi-chip modules and method of using same.
  2. Momenpour,Saeed; Brunelle,Steven J., Adapter for non-permanently connecting integrated circuit devices to multi-chip modules and method of using same.
  3. Saeed Momenpour ; Steven J. Brunelle, Adapter for non-permanently connecting integrated circuit devices to multi-chip modules and method of using same.
  4. Audet,Jean; Guerin,Luc; Landreville,Jean Luc; Audet,Gerald Pieree, Area array package with low inductance connecting device.
  5. Hougham, Gareth; McVicker, Gerard; Gu, Xiaoxiong; Kang, Sung K.; Libsch, Frank R.; Liu, Xiao H., Axiocentric scrubbing land grid array contacts and methods for fabrication.
  6. Hougham, Gareth; McVicker, Gerard; Gu, Xiaoxiong; Kang, Sung K.; Libsch, Frank R.; Liu, Xiao H., Axiocentric scrubbing land grid array contacts and methods for fabrication.
  7. Soejima Koji,JPX ; Senba Naoji,JPX, Bump structure and method for making the same.
  8. Ju, Ted, CPU and circuit board mounting arrangement.
  9. Hechtfischer, Gerd; Hohenester, Wilhelm; Huber, Rupert; Jünemann, Ralf; Pinta, Christian; Völk, Monika, Calibration unit for a measurement device.
  10. Dugas, Matthew Phillip; Ellison, Steven Brian; Wagner, Gregory Lawrence, Catch flexure systems, devices and methods.
  11. Kajiwara, Jiro; Wang, Huey-Ming, Chemical mechanical polishing apparatus and method having a rotating retaining ring.
  12. Lee, Jin-Yuan; Lin, Eric, Circuit component with conductive layer structure.
  13. Kacker, Karan; Sitaraman, Suresh K., Compliant off-chip interconnects for use in electronic packages and fabrication methods.
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  16. Zakel,Elke, Contact bump construction for the production of a connector construction for substrate connecting surfaces.
  17. Canella,Robert L., Device for establishing non-permanent electrical connection between an integrated circuit device lead element and a substrate.
  18. Canella,Robert L., Device for establishing non-permanent electrical connection between an integrated circuit device lead element and a substrate.
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  24. Mason, Jeffrey Walter; Alden, III, Wayne Stewart, Electrical interconnect device.
  25. Mason, Jeffery Walter; Alden, III, Wayne Stewart, Electrical interconnect device employing an array of conductive elastomer columns.
  26. Stutzman, A. Jay; Cram, Daniel P., Electrical testing apparatus having masked sockets and associated systems and methods.
  27. Hedler, Harry, Electronic configuration with flexible bonding pads.
  28. Haemer,Joseph Michael; Chong,Fu Chiung; Modlin,Douglas N., Enhanced compliant probe card systems having improved planarity.
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  30. Mok,Sammy; Chong,Fu Chiung; Milter,Roman, Enhanced stress metal spring contactor.
  31. Blair, James Leroy; Schreiber, Oswin M.; Smith, Jeffrey Thomas, Flexible interconnect cable for an electronic assembly.
  32. Blair, James Leroy; Smith, Jeffrey Thomas, Flexible interconnect cable having signal trace pairs and ground layer pairs disposed on opposite sides of a flexible dielectric.
  33. Blair, James Leroy; Schreiber, Oswin M.; Smith, Jeffrey Thomas, Flexible interconnect cable with first and second signal traces disposed between first and second ground traces so as to provide different line width and line spacing configurations.
  34. Conn, Robert O.; Carey, Steven J., Flip-chip package having thermal expansion posts.
  35. Bottoms, Wilmer R.; Chong, Fu Chiung; Mok, Sammy; Modlin, Douglas, High density interconnect system for IC packages and interconnect assemblies.
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  39. Kim, Hyun Joung; Lim, Taeg Ki; Yun, Ja Eun, Integrated circuit package system with thermo-mechanical interlocking substrates.
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  52. Canella,Robert L., Method of establishing non-permanent electrical connection between an integrated circuit device lead element and a substrate.
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  65. Distefano, Thomas H., Packaged microelectronic elements with enhanced thermal conduction.
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  67. Takekoshi, Kiyoshi, Probe card with pyramid shaped thin film contacts.
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  71. Mathieu, Gaetan L.; Eldridge, Benjamin N.; Grube, Gary W.; Larder, Richard A., Spring interconnect structures.
  72. Mathieu, Gaetan L.; Eldridge, Benjamin N.; Grube, Gary W.; Larder, Richard A., Spring interconnect structures.
  73. Mathieu,Gaetan L.; Eldridge,Benjamin N.; Grube,Gary W.; Larder,Richard A., Spring interconnect structures.
  74. Hwang, In Chul; Cho, Il Hwan; Kim, Ki Young, Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same.
  75. Balucani, Marco, System for contacting electronic devices and production processes thereof.
  76. Mok, Sammy; Chong, Fu Chiung, Systems for testing and packaging integrated circuits.
  77. Mok, Sammy; Chong, Fu Chiung; Milter, Roman, Systems for testing and packaging integrated circuits.
  78. Ito, Yugo, Terminal component and portable electronic device.
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