초록 ▼

An integrated circuit fabricated on a semiconductor chip is electrically connected through an array of pads to leads of a package; the pad array includes long pads exposed to first partially constricted openings and short pads exposed to second partially constricted openings and alternated with the

An integrated circuit fabricated on a semiconductor chip is electrically connected through an array of pads to leads of a package; the pad array includes long pads exposed to first partially constricted openings and short pads exposed to second partially constricted openings and alternated with the long pads, and the wide portions of the first partially constricted openings are offset from the wide portions of the adjacent second partially constricted openings so that the manufacturer arranges the long pads and the short pads at a fine pitch less than 40 microns.

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor device comprising:a substrate structure having an insulating layer,a plurality of first pads formed on said insulating layer and electrically connected to an integrated circuit;a plurality of second pads longer than said plurality of first pads, electrical

[ What is claimed is:] [1.] A semiconductor device comprising:a substrate structure having an insulating layer,a plurality of first pads formed on said insulating layer and electrically connected to an integrated circuit;a plurality of second pads longer than said plurality of first pads, electrically connected to said integrated circuit and alternated with said plurality of first pads on said insulating layer along a first virtual line;a protective layer covering said insulating layer, said plurality of first pads and said plurality of second pads, and formed witha plurality of first openings respectively associated with said plurality of first pads, said first openings having first narrow portions at an end of said first pads intersecting said first virtual line and first wide portions at another end of said first pads, wherein the width of said first wide portions is greater than the width of said first pads, anda plurality of second openings respectively associated with said plurality of second pads, said plurality of second openings having second narrow portions at an end of said second pads intersecting said first virtual line and second wide portions at another end of said second pads, wherein the width of said second wide portions is greater than the width of said second pads, and said second wide portions being offset from said first wide portions in longitudinal directions of said plurality of second pads perpendicular to said first virtual line.