초록 ▼

An image processing device which processes a portion of the decompression process including a lot of comparatively complex operations like an inverse discrete cosine transform by software with using a high-performance, general-purpose processor capable of parallel processing, and the other portion o

An image processing device which processes a portion of the decompression process including a lot of comparatively complex operations like an inverse discrete cosine transform by software with using a high-performance, general-purpose processor capable of parallel processing, and the other portion of the decompression process which is comparatively simple but requires frequent access to a memory, e.g., when other frame data is to be read out for processing of encoded interframe predictive image data, or is comparatively simple but substantially hard to process in parallel, e.g., when variable length coded pixel values are to be decoded, by hardware with the use of a specialized peripheral circuit.

대표청구항 ▼

[ What is claimed is:] [1.] An image processing device comprising:a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outpu

[ What is claimed is:] [1.] An image processing device comprising:a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit; anda data loader, connected to said processor, which includes a data reading unit for reading image data of fixed length codes, an adding unit, connected to the data reading unit, for adding image data of at least two adjacent pixels of the image data read by the data reading unit, and a data writing unit, connected to the adding unit, for writing the addition result by the adding unit into said processor,wherein said processor is configured to perform a process of decoding a first kind of image data of variable length codes to a second kind of image data of fixed length codes, a process of transforming the second kind of image data to a third kind of image data, a process of performing a prescribed operation between the third kind of image data and the addition result written by said data loader.