초록 ▼

A method is disclosed for forming inlaid copper interconnects in an insulating layer without the normally expected dishing that occurs after chemical-mechanical polishing of the excess copper. This is accomplished by forming a conformal blanket barrier layer over a substrate including a composite gr

A method is disclosed for forming inlaid copper interconnects in an insulating layer without the normally expected dishing that occurs after chemical-mechanical polishing of the excess copper. This is accomplished by forming a conformal blanket barrier layer over a substrate including a composite groove/hole structure already formed in an insulating layer and then growing a copper seed layer over the barrier layer. A layer of photoresist is next deposited over the substrate filling the composite structure. The photoresist layer, seed layer and the barrier layer are then removed by chemical-mechanical polishing, leaving the seed layer and the barrier layer on the inside walls of the composite structure, however. Then the photoresist is removed from the composite structure, and replaced, in its place, with electroless plated copper, which forms a dome-like protrusion extending from the composite structure. When the substrate is subjected to chemical-mechanical polishing in order to remove the excess copper, the dome-like structure prevents the dishing of the copper metal. In a second embodiment, the seed layer and the barrier layer are chemical-mechanical polished without first depositing a photoresist layer. Copper metal is next selectively formed by electroless plating having a dome-like protrusion, which in turn is removed by chemical-mechanical polishing without the detrimental formation of dishing in the copper metal.

대표청구항 ▼

[ What is claimed is:] [1.] A method of improving chemical-mechanical polishing (CMP) dishing comprising the steps of:providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon;forming a lower level dielectric (LLD) layer ov

[ What is claimed is:] [1.] A method of improving chemical-mechanical polishing (CMP) dishing comprising the steps of:providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon;forming a lower level dielectric (LLD) layer over said substrate;forming an etch-stop layer over said LLD layer;forming an upper level dielectric (ULD) layer over said etch-stop layer;forming a first photoresist layer over said ULD layer;patterning said first photoresist layer with a hole pattern;etching through said hole pattern in said first photoresist layer into said ULD layer;etching further said hole pattern into said etch-stop layer;removing said first photoresist layer from said substrate;forming a second photoresist layer over said substrate including said hole pattern;patterning said second photoresist layer with a conductive line groove pattern;etching through said conductive line groove in said second photoresist layer into said ULD layer until etch-stop layer is reached;etching further and transferring said hole pattern from said ULD layer into said LLD layer until a lower level said substructure of said substrate is reached thus forming a composite groove/hole structure;removing said second photoresist layer;forming a barrier layer on the walls, including the bottom wall, of said composite groove/hole structure;forming a seed layer over said barrier layer;forming a third photoresist layer over said substrate including said composite groove/hole structure;chemical-mechanical polishing said third photoresist layer, said seed layer and said barrier layer until ULD top surface is reached;removing said third photoresist layer from said composite groove/hole structure;forming metal in said composite groove/hole structure; andchemical-mechanical polishing said metal.