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Field programmable gate array with dedicated computer bus interface and method for configuring both 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0876909 (1997-06-13)
발명자 / 주소
  • New Bernard J.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Hoffman
인용정보 피인용 횟수 : 199  인용 특허 : 5

초록 ▼

A field programmable gate array is provided which has a programmable portion and a dedicated controller-interface circuit. The programmable portion includes conventional input/output (I/O) blocks and configurable logic blocks (CLBs). The controller-interface circuit allows the FPGA to be operably co

대표청구항 ▼

[ What is claimed is:] [1.] A field programmable gate array (FPGA) comprising:a dedicated bus controller-interface circuit for connecting to an external computer bus; anda programmable portion coupled to the bus controller-interface circuit, wherein the programmable portion is programmable by implie

이 특허에 인용된 특허 (5)

  1. Kean Thomas A.,GB6, Embedded memory for field programmable gate array.
    상세보기
  2. Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.
    상세보기
  3. Chatter Mukesh, High performance self modifying on-the-fly alterable logic FPGA, architecture and method.
    상세보기
  4. Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
    상세보기
  5. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
    상세보기

이 특허를 인용한 특허 (199)

  1. Hiscock, Dale, Adaptive routing to avoid non-repairable memory and logic defects on automata processor.
    상세보기
  2. Mar, Monte, Apparatus and method for programmable power management in a programmable analog circuit block.
    상세보기
  3. Atsatt, Sean R., Apparatus for configurable electronic circuitry and associated methods.
    상세보기
  4. Herron,Nigel G.; Thorne,Eric J.; Wang,Qingqi, Apparatus for testing an interconnecting logic fabric.
    상세보기
  5. Xu, Ning-Yi; Hsu, Feng-Hsiung; Gao, Rui; Cai, Xiong-Fei; Chen, Junyan, Automated feature selection based on rankboost for ranking.
    상세보기
  6. Sullam, Bert; Kutz, Harold; Mar, Monte; Thiagaragen, Eashwar; Williams, Timothy; Wright, David G., Autonomous control in a programmable system.
    상세보기
  7. Sarmah, Mrinal J., Booting of integrated circuits.
    상세보기
  8. Roe, Steve; Nemecek, Craig, Breakpoint control in an in-circuit emulation system.
    상세보기
  9. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
    상세보기
  10. Kryzak,Joseph Neil; Hoelscher,Aaron J.; Rock,Thomas E., Channel bonding of a plurality of multi-gigabit transceivers.
    상세보기
  11. Vorbach, Martin, Chip including memory element storing higher level memory data on a page by page basis.
    상세보기
  12. Wright, David G.; Williams, Timothy J., Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes.
    상세보기
  13. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
    상세보기
  14. Iwanczuk Roman ; Young Steven P. ; Schultz David P., Circuits and methods for operating a multiplexer array.
    상세보기
  15. Synder, Warren; Sullam, Bert, Clock driven dynamic datapath chaining.
    상세보기
  16. Nemecek, Craig, Conditional branching in an in-circuit emulation system.
    상세보기
  17. Snyder, Warren, Configurable input/output interface for a microcontroller.
    상세보기
  18. Douglass, Stephen M.; Ansari, Ahmad R., Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor.
    상세보기
  19. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
    상세보기
  20. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
    상세보기
  21. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat, Configuration of programmable IC design elements.
    상세보기
  22. Ananthiah, Umesh; Tran, Tramie; Freed, Jamie, Configuration sequence for programmable logic device.
    상세보기
  23. Douglass, Stephen M.; Ansari, Ahmad R., Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion.
    상세보기
  24. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  25. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  26. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  27. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
    상세보기
  28. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
    상세보기
  29. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing system having integrated pipelined array data processor.
    상세보기
  30. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
    상세보기
  31. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
    상세보기
  32. Synder, Warren; Sullam, Bert, Dynamically configurable and re-configurable data path.
    상세보기
  33. Steven P. Young, Expandable interconnect structure for FPGAS.
    상세보기
  34. Nemecek, Craig; Roe, Steve, External interface for event architecture.
    상세보기
  35. Zhu, Jinghui; Ni, Jin; Shen, Ju; Wang, Tong-Sheng, FIFO memory architecture.
    상세보기
  36. Schultz, David P., FPGA and embedded circuitry initialization and processing.
    상세보기
  37. Iwanczuk Roman ; Young Steven P. ; Schultz David P., FPGA having fast configuration memory data readback.
    상세보기
  38. Xu, Ning-Yi; Cai, Xiong-Fei; Gao, Rui; Yan, Jing; Hsu, Feng-Hsiung, Field-programmable gate array based accelerator system.
    상세보기
  39. Xu, Ning-Yi; Cai, Xiong-Fei; Hsu, Feng-Hsiung, Field-programmable gate array based accelerator system.
    상세보기
  40. Xu, Ning-yi; Hsu, Feng-Hsiung; Cai, Xiong-Fei, Field-programmable gate array based accelerator system.
    상세보기
  41. Cory,Warren E.; Ghia,Atul V., Flexible channel bonding and clock correction operations on a multi-block data path.
    상세보기
  42. Pleis, Mathew A; Ogami, Kenneth Y; Zhaksilikov, Marat, Graphical user interface for dynamically reconfiguring a programmable device.
    상세보기
  43. Pleis, Matthew A.; Ogami, Kenneth Y.; Zhaksilikov, Marat, Graphical user interface for dynamically reconfiguring a programmable device.
    상세보기
  44. Anderson, Doug, Graphical user interface with user-selectable list-box.
    상세보기
  45. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
    상세보기
  46. Menon,Suresh M.; Ghia,Atul V.; Cory,Warren E.; Sasaki,Paul T.; Freidin,Philip M.; Asuncion,Santiago G.; Costello,Philip D.; Vadi,Vasisht M.; Bekele,Adebabay M.; Verma,Hare K., High speed configurable transceiver architecture.
    상세보기
  47. Agrawal, Om P.; Zhu, Jinghui; Chi, Kuang; Chen, ChienKuang, High speed interface for a programmable interconnect circuit.
    상세보기
  48. Agrawal, Om P.; Zhu, Jinghui; Chi, Kuang; Chen, ChienKuang, High speed interface for a programmable interconnect circuit.
    상세보기
  49. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  50. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  51. Nemecek, Craig; Roe, Steve, In-circuit emulator and pod synchronized boot.
    상세보기
  52. Seguine, Dennis R., Input/output multiplexer bus.
    상세보기
  53. Sequine, Dennis R., Input/output multiplexer bus.
    상세보기
  54. Gan, Andy H.; Herron, Nigel G., Insertable block tile for interconnecting to a device embedded in an integrated circuit.
    상세보기
  55. Wingen, Neal T., Integrated circuit arrangement with feature control.
    상세보기
  56. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
    상세보기
  57. Bradley L. Taylor, Local memory unit system with global access for use on reconfigurable chips.
    상세보기
  58. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  59. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  60. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  61. Atta, Islam Mohamed Hatem Abdulfattah Mohamed, Logic repository service.
    상세보기
  62. Atta, Islam Mohamed Hatem Abdulfattah Mohamed; Pettey, Christopher Joseph; Bshara, Nafea; Khan, Asif; Davis, Mark Bradley; Tandon, Prateek, Logic repository service using encrypted configuration data.
    상세보기
  63. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
    상세보기
  64. Klein, Dean A., Memory management for a hierarchical memory system.
    상세보기
  65. Klein, Dean A., Memory management for a hierarchical memory system.
    상세보기
  66. Cory,Warren E., Method and apparatus for operating a transceiver in different data rates.
    상세보기
  67. Douglass,Stephen M.; Ansari,Ahmad R., Method and apparatus for processing data with a programmable gate array using fixed and programmable processors.
    상세보기
  68. Gan, Andy H., Method and apparatus for routing interconnects to devices with dissimilar pitches.
    상세보기
  69. Ansari,Ahmad R.; Vashi,Mehul R., Method and apparatus for synchronized buses.
    상세보기
  70. Fang, Ying, Method and apparatus for testing an embedded device.
    상세보기
  71. Herron,Nigel G.; Thorne,Eric J.; Wang,Qingqi, Method and apparatus for testing circuitry embedded within a field programmable gate array.
    상세보기
  72. Burnley,Richard P.; Oda,Shizuka; Gan,Andy H., Method and apparatus for timing modeling.
    상세보기
  73. Oda,Shizuka; Burnley,Richard P., Method and apparatus for timing modeling.
    상세보기
  74. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
    상세보기
  75. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
    상세보기
  76. Yin, Robert; Vashi, Mehul R., Method and system for controlling default values of flip-flops in PGA/ASIC-based designs.
    상세보기
  77. Sanchez, Reno L.; Linn, John H., Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC).
    상세보기
  78. Sanchez, Reno L.; Linn, John H., Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC).
    상세보기
  79. Sanchez,Reno L.; Linn,John H., Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC).
    상세보기
  80. Schultz,David P., Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC).
    상세보기
  81. Vorbach, Martin, Method for debugging reconfigurable architectures.
    상세보기
  82. Vorbach, Martin, Method for debugging reconfigurable architectures.
    상세보기
  83. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
    상세보기
  84. Vorbach,Martin, Method for debugging reconfigurable architectures.
    상세보기
  85. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
    상세보기
  86. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
    상세보기
  87. Perrin, Jon; Seguine, Dennis, Method for parameterizing a user module.
    상세보기
  88. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
    상세보기
  89. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
    상세보기
  90. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
    상세보기
  91. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
    상세보기
  92. Douglass, Stephen M., Method of designing integrated circuit having both configurable and fixed logic circuitry.
    상세보기
  93. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
    상세보기
  94. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Method of processing data with an array of data processors according to application ID.
    상세보기
  95. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  96. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  97. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  98. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  99. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  100. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
    상세보기
  101. Sung, Sang-Kyung; Lee, Ji-Hye; Park, Sung-Jin, Method, user equipment and system for providing simultaneous PoC multimedia services session by session.
    상세보기
  102. Brown, David R.; Noyes, Harold B; Bains, Inderjit S., Methods and apparatuses for providing data received by a plurality of state machine engines.
    상세보기
  103. Brown, David R.; Noyes, Harold B; Bains, Inderjit S., Methods and apparatuses for providing data received by a state machine engine.
    상세보기
  104. Noyes, Harold B; Brown, David R., Methods and devices for programming a state machine engine.
    상세보기
  105. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  106. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  107. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  108. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
    상세보기
  109. Vorbach, Martin, Methods and devices for treating and/or processing data.
    상세보기
  110. Lee,Andy L.; McClintock,Cameron; Johnson,Brian; Cliff,Richard; Reddy,Srinivas; Lane,Chris; Leventis,Paul; Betz,Vaughn Timothy; Lewis,David, Methods for designing PLD architectures for flexible placement of IP function blocks.
    상세보기
  111. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
    상세보기
  112. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
    상세보기
  113. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
    상세보기
  114. Snyder, Warren, Microcontroller programmable system on a chip with programmable interconnect.
    상세보기
  115. Snyder, Warren S, Microcontroller programmable system on a chip with programmable interconnect.
    상세보기
  116. McDonald, John; Pearson, Jon; Ogami, Kenneth; Anderson, Doug, Model for a hardware device-independent method of defining embedded firmware for programmable systems.
    상세보기
  117. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.
    상세보기
  118. Vorbach, Martin, Multi-processor with selectively interconnected memory units.
    상세보기
  119. Muthujumaraswathy Kumaraguru ; Rostoker Michael D., Multimedia interface having a multimedia processor and a field programmable gate array.
    상세보기
  120. Muthujumaraswathy, Kumaraguru; Rostoker, Michael D., Multimedia interface having a processor and reconfigurable logic.
    상세보기
  121. Vorbach, Martin, Multiprocessor having associated RAM units.
    상세보기
  122. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.
    상세보기
  123. Sasaki,Paul T.; Menon,Suresh M.; Ghia,Atul V.; Cory,Warren E.; Verma,Hare K.; Freidin,Philip M., Network physical layer with embedded multi-standard CRC generator.
    상세보기
  124. Kutz, Harold, Numerical band gap.
    상세보기
  125. Brown, Brian Lewis, Overflow detection and correction in state machine engines.
    상세보기
  126. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
    상세보기
  127. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
    상세보기
  128. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
    상세보기
  129. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
    상세보기
  130. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Christopher; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
    상세보기
  131. Snyder, Warren S.; Mar, Monte, PSOC architecture.
    상세보기
  132. Snyder, Warren; Mar, Monte, PSOC architecture.
    상세보기
  133. Snyder, Warren S.; Mar, Monte, PSoC architecture.
    상세보기
  134. Snyder, Warren S.; Mar, Monte, PSoC architecture.
    상세보기
  135. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
    상세보기
  136. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
    상세보기
  137. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
    상세보기
  138. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
    상세보기
  139. Ogami, Kenneth Y., Power management architecture, method and configuration system.
    상세보기
  140. Ogami, Kenneth Y., Power management architecture, method and configuration system.
    상세보기
  141. Vorbach,Martin; M체nch,Robert, Process for automatic dynamic reloading of data flow processors (DFPS) and units with two-or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like).
    상세보기
  142. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
    상세보기
  143. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
    상세보기
  144. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
    상세보기
  145. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
    상세보기
  146. Schultz,David P.; Douglass,Stephen M.; Young,Steven P.; Herron,Nigel G.; Vashi,Mehul R.; Sowards,Jane W., Programmable gate array and embedded circuitry initialization and processing.
    상세보기
  147. Douglass, Stephen M.; Young, Steven P.; Herron, Nigel G.; Vashi, Mehul R.; Sowards, Jane W., Programmable gate array having interconnecting logic to support embedded fixed logic circuitry.
    상세보기
  148. Ansari, Ahmad R., Programmable interactive verification agent.
    상세보기
  149. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
    상세보기
  150. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
    상세보기
  151. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
    상세보기
  152. Groen,Eric D.; Boecker,Charles W.; Black,William C.; Irwin,Scott A.; Kryzak,Joseph N.; Chen,Yiqin; Jenkins,Andrew G.; Hoelscher,Aaron J., Programmable logic device including programmable multi-gigabit transceivers.
    상세보기
  153. Snyder, Warren, Programmable microcontroller architecture.
    상세보기
  154. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).
    상세보기
  155. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).
    상세보기
  156. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte, Programmable sigma-delta analog-to-digital converter.
    상세보기
  157. Snyder, Warren; Maheshwari, Dinesh; Ogami, Kenneth; Hastings, Mark, Providing hardware independence to automate code generation of processing device firmware.
    상세보기
  158. Brown, David R.; Noyes, Harold B; Bains, Inderjit S., Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine.
    상세보기
  159. Vorbach, Martin, Reconfigurable elements.
    상세보기
  160. Vorbach, Martin, Reconfigurable elements.
    상세보기
  161. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
    상세보기
  162. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
    상세보기
  163. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  164. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  165. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  166. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  167. Vorbach,Martin, Reconfigurable sequencer structure.
    상세보기
  168. Pleis, Matthew A.; Sullam, Bert; Lesher, Todd, Reconfigurable testing system and method.
    상세보기
  169. Casselman, Steven Mark, Reconfiguration of an accelerator module having a programmable logic device.
    상세보기
  170. Vorbach, Martin; Bretz, Daniel, Router.
    상세보기
  171. Vorbach,Martin; Bretz,Daniel, Router.
    상세보기
  172. Vorbach,Martin; M？nch,Robert, Run-time reconfiguration method for programmable units.
    상세보기
  173. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
    상세보기
  174. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
    상세보기
  175. Mattice, Harold E.; Wilder, Richard; Griswold, Chauncey W., Secured verification of configuration data for field programmable gate array devices.
    상세보기
  176. Nemecek, Craig, Sleep and stall in an in-circuit emulation system.
    상세보기
  177. Wicker, Jr., David J., State machine in a programmable logic device.
    상세보기
  178. Ogami, Kenneth; Best, Andrew; Zhaksilikov, Marat, System and method for controlling a target device.
    상세보기
  179. Anderson, Douglas H.; Ogami, Kenneth Y., System and method for dynamically generating a configuration datasheet.
    상세보기
  180. Ogami, Kenneth Y.; Hood, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
    상세보기
  181. Ogami, Kenneth Y.; Hood, III, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
    상세보기
  182. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
    상세보기
  183. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
    상세보기
  184. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, III, Frederick Redding, Techniques for generating microcontroller configuration information.
    상세보기
  185. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, Rick, Techniques for generating microcontroller configuration information.
    상세보기
  186. Venkataraman, Garthik; Kutz, Harold; Mar, Monte, Temperature sensor with digital bandgap.
    상세보기
  187. Herron,Nigel G.; Thorne,Eric J.; Wang,Qingqi; Correale, Jr.,Anthony; Dick,Thomas Anderson, Testing a programmable logic device with embedded fixed logic using a scan chain.
    상세보기
  188. Yin, Robert, Testing address lines of a memory controller.
    상세보기
  189. Yin,Robert, Testing address lines of a memory controller.
    상세보기
  190. Burnley, Richard P., Timing performance analysis.
    상세보기
  191. Burnley,Richard P., Timing performance analysis.
    상세보기
  192. Beard, Paul; Woodings, Ryan Winfield, Touch wake for electronic devices.
    상세보기
  193. Snyder, Warren; Sullam, Bert; Mohammed, Haneef, Universal digital block interconnection and channel routing.
    상세보기
  194. Preiss, Frank; Staudt, Christian; Hartung, Joerg, Universal serial bus interfacing using FIFO buffers.
    상세보기
  195. Douglass, Stephen M.; Sastry, Prasad L.; Vashi, Mehul R.; Yin, Robert, User configurable memory system having local and global memory blocks.
    상세보기
  196. Ansari, Ahmad R.; Douglass, Stephen M.; Vashi, Mehul R.; Young, Steven P., User configurable on-chip memory system.
    상세보기
  197. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Doug, User interface for efficiently browsing an electronic document using data-driven tabs.
    상세보기
  198. Noyes, Harold B; Brown, David R.; Glendenning, Paul, Validation of a symbol response memory.
    상세보기
  199. Sivadasan, Mohandas Palatholmana; Rohilla, Gajendar, Voltage controlled oscillator delay cell and method.
    상세보기

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