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Constraining ring for use in electronic packaging 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/02
  • H05K-001/03
  • H05K-001/09
  • H05K-001/16
출원번호 US-0195054 (1998-11-18)
발명자 / 주소
  • Budnaitis John J.
  • Fischer Paul J.
  • Hanson David A.
  • Noddin David B.
  • Sylvester Mark F.
  • Petefish William George
출원인 / 주소
  • W. L. Gore & Associates, Inc.
대리인 / 주소
    Genco, Jr.
인용정보 피인용 횟수 : 19  인용 특허 : 24

초록

A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors a

대표청구항

[ What is claimed is:] [1.] A chip package comprising:an interconnect substrate having a coefficient of thermal expansion (CTE), a modulus of elasticity, first and second opposite surfaces, peripheral edges, and a central chip mounting area on the first surface;an adhesive layer; anda substantially

이 특허에 인용된 특허 (24)

  1. Swamy N. Deepak (Austin TX), Apparatus and method of making laminate an embedded conductive layer.
  2. Howard James R. (Los Gatos CA) Lucas Gregory L. (Newark CA), Capacitor laminate for use in capacitive printed circuit boards and methods of manufacture.
  3. Howard James R. (Sacramento CA) Lucas Gregory L. (Newark CA), Capacitor laminate for use in capacitive printed circuit boards and methods of manufacture.
  4. Howard James R. (Sacramento CA) Lucas Gregory L. (Newark CA), Capacitor laminate for use in capacitive printed circuit boards and methods of manufacture.
  5. Evelove Leon G. (Los Angeles County CA) Leone John S. (Orange County CA) White Don E. (Los Angeles County CA), Ceramic circuit board mounted in housing and method of fabrication thereof.
  6. Beppu Henry (San Diego CA) Kushuhara Toshi (San Diego CA) Nomura Aki (San Diego CA), Ceramic-glass integrated circuit package with ground plane.
  7. James Christopher D. (La Costa CA) McNeal Norman E. (Carlsbad CA), Easily repairable, low cost, high speed electromechanical assembly of integrated circuit die.
  8. Bonafino Edward J. (Endwell NY) Carpenter Richard W. (Johnson City NY) Lueck Peter J. (Leonberg NY DEX) Summa William J. (Endwell NY) Wang David W. (Vestal NY), Electronic circuit packages with tear resistant organic cores.
  9. Morgan Charles G. (Laurens SC), Electronic substrate article and method of preparation.
  10. Fischer Paul (Wilmington DE), High capacitance laminates.
  11. Lucas Gregory L. (Newark CA), In situ method for forming a capacitive PCB.
  12. Belke ; Jr. Robert E. (Clay NY) Trojanowski George F. (Baldwinsville NY) Zakraysek Louis (Cicero NY), Metal matrix composite and structure using metal matrix composites for electronic applications.
  13. Bhatt Ashwinkumar C. (Endicott NY) Duffy Thomas P. (Endicott NY) Knight Jeffrey A. (Endwell NY) Walsh James P. (Vandling PA), Method of construction for multi-tiered cavities used in laminate carriers.
  14. Greenman Norman L. ; Hernandez Jorge M. ; Panicker M. P. Ramachandra, Method of making microwave circuit package.
  15. Wein Deborah S. ; Anderson Paul M. ; Lindner Alan W. ; Goetz Martin ; Babiarz Joseph, Microelectronics package.
  16. Hanson John R. (Richmond MA) Hauser James L. (Lenox MA) Kilfeather ; Jr. James F. (Pittsfield MA) Hendriks Hendrik B. (Becket MA), Multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion.
  17. Leibowitz Joseph D. (Culver City CA), Multilayer printed circuit board structure.
  18. Smith Brenda K. (Scottsdale AZ), Multiple power/ground planes for tab.
  19. Okada Masaaki (Itami JPX) Usuki Tosio (Itami JPX), Packaged semiconductor device including shielded inner walls.
  20. Mortimer ; Jr. William P. (New Castle DE), Polytetrafluoroethylene film.
  21. Hatakeyama Minoru (Sakuragaokanishi JPX) Moriya Kosuke (Okayama JPX) Komada Ichiro (Okayama JPX), Printed circuit board base material.
  22. Bowman Jeffery B. (Flagstaff AZ) Hubis Daniel E. (Elkton MD) Lewis James D. (Flagstaff AZ) Newman Stephen C. (Flagstaff AZ) Staley Richard A. (Flagstaff AZ), Process for producing a high strength porous polytetrafluoroethylene product having a coarse microstructure.
  23. Gore Robert W. (Newark DE), Process for producing porous products.
  24. Ota Kazuhide (Okazaki JPX) Abe Susumu (Toyota JPX), Process for producing ultra-fine ceramic particles.

이 특허를 인용한 특허 (19)

  1. Colgan,Evan G.; Edwards,David L.; Fasano,Benjamin V.; Sikka,Kamal K.; Zitz,Jeffrey A.; Zou,Wei, Chip package having chip extension and method.
  2. Chengalva,Suresh K.; Ihms,David W.; Myers,Bruce A., Circuit board with localized stiffener for enhanced circuit component reliability.
  3. Balakrishnan, Karthik; Bedell, Stephen W.; Hashemi, Pouya; Reznicek, Alexander, Deformable and flexible capacitor.
  4. Topacio, Roden; Zbrzezny, Adam, Die substrate with reinforcement structure.
  5. Topacio, Roden; Zbrzezny, Adam, Die substrate with reinforcement structure.
  6. Tsuduki, Koji; Suzuki, Takanori; Kosaka, Tadashi; Matsuki, Yasuhiro; Hasegawa, Shin; Komori, Hisatane; Kurihara, Yasushi; Ito, Fujio; Notsu, Kazuya, Electronic component and electronic apparatus.
  7. Tsuduki, Koji; Suzuki, Takanori; Kosaka, Tadashi; Matsuki, Yasuhiro; Hasegawa, Shin; Ito, Fujio; Komori, Hisatane; Kurihara, Yasushi, Electronic component, electronic module, their manufacturing methods, mounting member, and electronic apparatus.
  8. Tsuduki, Koji; Suzuki, Takanori; Kosaka, Tadashi; Matsuki, Yasuhiro; Hasegawa, Shin; Ito, Fujio; Komori, Hisatane; Kurihara, Yasushi, Electronic component, mounting member, electronic apparatus, and their manufacturing methods.
  9. Murari, Bruno; Mastromatteo, Ubaldo; Vigna, Benedetto, Electronic semiconductor device having a thermal spreader.
  10. Voegerl, Andreas; Liebl, Tilo; Bauer, Gerhard; Gebhardt, Marion; Wenk, Alexander; Wieczorek, Matthias; Henniger, Juergen; Baumann, Karl-Heinz, Flexible printed board.
  11. Dolci, Dominic E.; Smeenge, James G.; Diep, Vinh H.; Goh, Chiew-Siang, Heat sinking and electromagnetic shielding structures.
  12. Hwang, Seung Jae, Hybrid insulation sheet and electronic apparatus using the same.
  13. Sylvester, Mark F.; Hanson, David A.; Petefish, William G., Interconnect module with reduced power distribution impedance.
  14. Li, Shidong, Limiting electronic package warpage.
  15. Li, Shidong, Limiting electronic package warpage with semiconductor chip lid and lid-ring.
  16. Yamashita, Yoshihisa; Hirano, Koichi; Nakatani, Seiichi, Power module and method of manufacturing the same.
  17. Yamashita,Yoshihisa; Hirano,Koichi; Nakatani,Seiichi, Power module and method of manufacturing the same.
  18. Merte, Donald A.; Weiss, Thomas, Universal clamping fixture to maintain laminate flatness during chip join.
  19. Merte, Donald A.; Weiss, Thomas, Universal clamping fixture to maintain laminate flatness during chip join.
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