초록 ▼

Methods for forming via holes in inter-level dielectric layers for via connections to underlying electrodes are described. The underlying electrodes do not have electrode pads or enlarged areas of the electrode to contact the conductive material in the via hole. The method avoids the problems of ove

Methods for forming via holes in inter-level dielectric layers for via connections to underlying electrodes are described. The underlying electrodes do not have electrode pads or enlarged areas of the electrode to contact the conductive material in the via hole. The method avoids the problems of oversize vias and mis-aligned vias. One of the embodiments uses extra wide dielectric spacers formed in two steps on the sidewalls of the underlying electrodes. The spacers provide an effective electrode width greater than the actual width of the electrode thereby increasing the tolerance for both the size and the alignment of the via holes. Another embodiment uses alternate layers of two dielectric materials and etching methods which etch each of the two materials selectively. The dielectric material which is not etched in each step serves as an etch stop layer.

대표청구항 ▼

[ What is claimed is:] [1.] A method of forming via connections, comprising the steps of:providing a substrate having a layer of first dielectric formed thereon;forming electrodes from a first conducting material, each said electrode having a top surface and sidewalls, on said layer of first dielect

[ What is claimed is:] [1.] A method of forming via connections, comprising the steps of:providing a substrate having a layer of first dielectric formed thereon;forming electrodes from a first conducting material, each said electrode having a top surface and sidewalls, on said layer of first dielectric, wherein said top surfaces of said electrodes have a number of contact regions;forming a first layer of second dielectric on substrate thereby covering said electrodes;etching back said first layer of said second dielectric using a first etching means thereby forming first spacers of said second dielectric on said sidewalls of said electrodes;forming a second layer of said second dielectric on said substrate thereby covering said first spacers of said second dielectric on said sidewalls of said electrodes;etching back said second layer of said second dielectric using a second etching means thereby forming second spacers of said second dielectric on said first spacers of said second dielectric and removing all of said second dielectric from said top surfaces of said electrodes, wherein said second spacers formed on said first spacers have a total spacer width;forming a layer of third dielectric on said substrate thereby covering said electrodes, said first spacers of said second dielectric and said second spacers of said second dielectric;etching via holes in said layer of third dielectric using a third etching means thereby removing said third dielectric from part or all of said contact regions of said electrodes, wherein said third etching means provides an etching rate for said third dielectric at least ten times greater than the etching rate for said second dielectric; andfilling said via holes with a second conducting material.