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Resonance tunnel device

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/06
출원번호 US-0175505 (1998-10-20)
우선권정보 JP-0044492 (1996-03-01)
발명자 / 주소
  • Yuki Koichiro,JPX
  • Morita Kiyoyuki,JPX
  • Morimoto Kiyoshi,JPX
  • Hirai Yoshihiko,JPX
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd., JPX
대리인 / 주소
    Ratner & Prestia
인용정보 피인용 횟수 : 54  인용 특허 : 11

초록

The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pa

대표청구항

[ What is claimed is:] [1.] A semiconductor device comprising:a double barrier structure including a silicon thin plate having side walls and extending in a first direction, and a pair of first oxide films formed on the side walls of the silicon thin plate; anda second oxide film formed to cover the

이 특허에 인용된 특허 (11)

  1. Higurashi Hitoshi (Yokohama JPX) Toriumi Akira (Yokohama JPX) Yamaguchi Fumiko (Noda JPX) Kawamura Kiyoshi (Tokyo JPX) Hubler Alfred (Urbana IL), Correlation tunnel device.
  2. Hirai Yoshihiko (Osaka JPX) Morimoto Kiyoshi (Neyagawa JPX) Terui Yasuaki (Neyagawa JPX) Niwa Masaaki (Hirakata JPX) Yasui Juro (Toyonaka JPX) Okada Kenji (Suita JPX) Udagawa Masaharu (Tokyo JPX) Yuk, Electrically insulated silicon structure and producing method therefor.
  3. Yen Yung-Chau (San Jose CA), Metallization technique for integrated circuit structures.
  4. Lee Hae-Gwon (Daejeon KRX) Lee Jae-Jin (Daejeon KRX) Kim Bo-Woo (Daejeon KRX), Method for fabricating quantum wire laser diode.
  5. Kanazawa Kunihiko (Toyonaka JPX) Kazumura Masaru (Takatsuki JPX), Method for manufacturing a perpendicular sidewalled metal layer on a substrate.
  6. Yuki Koichiro (Neyagawa JPX) Hirai Yoshihiko (Osaka JPX) Morimoto Koyoshi (Neyagawa JPX) Niwa Masaaki (Hirakata JPX) Yasui Juro (Toyonaka JPX) Okada Kenji (Suita JPX) Udagawa Masaharu (Tokyo JPX), Method for producing quantization functional device utilizing a resonance tunneling effect.
  7. Okada Kenji (Suita JPX) Terui Yasuaki (Neyagawa JPX) Yasui Juro (Toyonaka JPX) Hirai Yoshihiko (Osaka JPX) Niwa Masaaki (Hirakata JPX) Wada Atsuo (Suita JPX) Morimoto Kiyoshi (Neyagawa JPX), Method of fabricating a quantum device.
  8. Seabaugh Alan C. (Richardson TX) Hosack Harold H. (Dallas TX), Method of forming implanted silicon resonant tunneling barriers.
  9. Uenoyama Takeshi (Kyoto JPX) Kumabuchi Yasuhito (Osaka JPX), Nonlinear element and bistable memory device.
  10. Takahashi Takahiko (Tokyo JPX) Itoh Funikazu (Fujisawa JPX) Shimase Akira (Yokohama JPX) Yamaguchi HIroshi (Fujisawa JPX) Hongo Mikio (Yokohama JPX) Haraichi Satoshi (Yokohama JPX), Semiconductor integrated circuit device and process for producing the same.
  11. Lux, Robert A.; Harvey, James F., Variable lateral quantum confinement transistor.

이 특허를 인용한 특허 (54)

  1. King, Tsu-Jae, Adaptive negative differential resistance device.
  2. King,Tsu Jae; Liu,David K. Y., CMOS compatible process for making a charge trapping device.
  3. King, Tsu-Jae; Liu, David K.Y., CMOS compatible process for making a tunable negative differential resistance (NDR) device.
  4. King, Tsu-Jae; Liu, David K. Y., CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same.
  5. King, Tsu-Jae; Liu, David K. Y., CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same.
  6. Tsu-Jae, King, Charge pump for negative differential resistance transistor.
  7. King,Tsu Jae; Liu,David K. Y., Charge trapping device.
  8. King, Tsu-Jae; Liu, David K. Y., Charge trapping device and method for implementing a transistor having a configurable threshold.
  9. Tsu-Jae King ; David K. Y. Liu, Charge trapping device and method for implementing a transistor having a negative differential resistance mode.
  10. King, Tsu-Jae, Charge trapping device and method of forming the same.
  11. King,Tsu Jae, Charge trapping device and method of forming the same.
  12. Tsu-Jae, King, Charge trapping pull up element.
  13. King, Tsu-Jae, Enhanced read and write methods for negative differential resistance (NDR) based memory device.
  14. King,Tsu Jae, Enhanced read and write methods for negative differential resistance (NDR) based memory device.
  15. Tsu-Jae, King, Field effect transistor pull-up/load element.
  16. King, Tsu-Jae, Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET.
  17. King,Tsu Jae, Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET.
  18. King,Tsu Jae, Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs).
  19. Barnes, Ted W.; Chavarria, Victorio; Sudyka, William J.; Ghozeil, Adam; Emery, Timothy R., Measurement of etching.
  20. Barnes,Ted W.; Chavarria,Victorio; Sudyka,William J.; Ghozeil,Adam; Emery,Timothy R., Measurement of etching.
  21. King, Tsu-Jae, Memory cell using negative differential resistance field effect transistors.
  22. King, Tsu-Jae; Liu, David K. Y., Method for configuring a device to include a negative differential resistance (NDR) characteristic.
  23. King, Tsu-Jae, Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode.
  24. King, Tsu-Jae; Liu, David K. Y., Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process.
  25. King, Tsu-Jae, Method of forming a negative differential resistance device.
  26. King,Tsu Jae, Method of forming a negative differential resistance device.
  27. King,Tsu Jae, Method of forming a negative differential resistance device.
  28. King,Tsu Jae, Method of making adaptive negative differential resistance device.
  29. King,Tsu Jae, Method of making memory cell utilizing negative differential resistance devices.
  30. King, Tsu-Jae, Method of orperating a dual mode FET & logic circuit having negative differential resistance mode.
  31. King, Tsu-Jae, Methods of testing/stressing a charge trapping device.
  32. King,Tsu Jae, Methods of testing/stressing a charge trapping device.
  33. King, Tsu-Jae, Negative differential resistance (NDR) based memory device with reduced body effects.
  34. King, Tsu-Jae; Liu, David K. Y., Negative differential resistance (NDR) device and method of operating same.
  35. King, Tsu-Jae, Negative differential resistance (NDR) element and memory with reduced soft error rate.
  36. King, Tsu-Jae, Negative differential resistance (NDR) element and memory with reduced soft error rate.
  37. King, Tsu-Jae, Negative differential resistance (NDR) elements and memory device using the same.
  38. King,Tsu Jae, Negative differential resistance (NDR) elements and memory device using the same.
  39. King, Tsu-Jae, Negative differential resistance (NDR) memory cell with reduced soft error rate.
  40. King, Tsu-Jae, Negative differential resistance (NDR) memory device with reduced soft error rate.
  41. Tsu-Jae, King, Negative differential resistance field effect transistor (NDR-FET) and circuits using the same.
  42. King,Tsu Jae, Negative differential resistance field effect transistor for implementing a pull up element in a memory cell.
  43. King, Tsu-Jae, Negative differential resistance load element.
  44. Tsu-Jae, King, Negative differential resistance pull up element.
  45. Liu, Tsu-Jae King, Negative differential resistance pull up element for DRAM.
  46. King, Tsu Jae, Process for controlling performance characteristics of a negative differential resistance (NDR) device.
  47. King, Tsu-Jae, Process for controlling performance characteristics of a negative differential resistance (NDR) device.
  48. King,Tsu Jae, Process for controlling performance characteristics of a negative differential resistance (NDR) device.
  49. King, Tsu-Jae, Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects.
  50. King,Tsu Jae, Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects.
  51. Kato, Takahisa; Shimada, Yasuhiro, Silicon processing method and silicon substrate with etching mask.
  52. King,Tsu Jae, Two terminal silicon based negative differential resistance device.
  53. King, Tsu-Jae; Liu, David K. Y., Variable threshold semiconductor device and method of operating same.
  54. King,Tsu Jae, Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device.
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