초록 ▼

The systems and methods described herein relate to LED systems capable of generating light, such as for illumination or display purposes. The light-emitting LEDs may be controlled by a processor to alter the brightness and/or color of the generated light, e.g., by using pulse-width modulated signals

The systems and methods described herein relate to LED systems capable of generating light, such as for illumination or display purposes. The light-emitting LEDs may be controlled by a processor to alter the brightness and/or color of the generated light, e.g., by using pulse-width modulated signals. Thus, the resulting illumination may be controlled by a computer program to provide complex, predesigned patterns of light in virtually any environment.

대표청구항 ▼

[ We claim:] [1.] Light apparatus comprising:a power terminal;at least one LED coupled to the power terminal;a current sink coupled to the at least one LED, the current sink comprising an input responsive to an activation signal enables flow of current through the current sink;an addressable control

[ We claim:] [1.] Light apparatus comprising:a power terminal;at least one LED coupled to the power terminal;a current sink coupled to the at least one LED, the current sink comprising an input responsive to an activation signal enables flow of current through the current sink;an addressable controller having an alterable address, the controller coupled to the input and having timing means for generating the activation signal for a predefined portion of a timing cycle;the addressable controller further comprising means for receiving data corresponding to the alterable address and indicative of the predefined portion of the timing cycle:a second LED coupled to the power terminal and the current sink;the current sink comprising a second input corresponding to the second LED and responsive to a second activation signal;the addressable controller comprising second timing means for generating the second activation signal for a second predefined portion of the timing cycle, and further comprising second means for receiving data corresponding to the alterable address and indicative of the second predefined portion of a timing cycle.