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Automatic semiconductor wafer sorter/prober with extended optical inspection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/26
출원번호 US-0886066 (1997-07-02)
발명자 / 주소
  • Fredriksen T. Roland
  • Chapman Robert L.
출원인 / 주소
  • Scanis, Inc.
대리인 / 주소
    Flehr Hohbach Test Albritton & Herbert LLP
인용정보 피인용 횟수 : 53  인용 특허 : 11

초록

A method and apparatus for visually inspecting and sorting semiconductor wafers and the individual microcircuits or chips thereon. The preferred embodiment employs a scanner to obtain a virtual reality image of the wafer and all chips are identified and sorted by applying high-speed image processing

대표청구항

[ We claim:] [1.] In a method for investigating electronic circuit devices for manufacturing defects, the steps of:(a) converting intuitive criteria used to investigate an electronic circuit device for manufacturing defects to specific numerical criteria;(b) programming a computer with said criteria

이 특허에 인용된 특허 (11)

  1. Rohrbaugh John G. (Fort Collins CO) Baker Thomas H. (Loveland CO) Bennett Michael J. (Wellington CO) Gil Mercedes E. (Fort Collins CO) Proulx Robert W. (Fort Collins CO), Apparatus and method for displaying wafer test results in real time.
  2. Specht Donald F. (Los Altos CA) Wihl Tim S. (San Jose CA) Young Scott A. (Scotts Valley CA) Hager ; Jr. James J. (San Jose CA) Lutzker Matthew B. (Menlo Park CA), Automatic photomask and reticle inspection method and apparatus including improved defect detector and alignment sub-sys.
  3. Kobayashi Kenichi (Tokyo JPX) Matsui Shougo (Sagamihara JPX), Dimension checking method.
  4. Falk Robert Aaron, Method and apparatus for imaging semiconductor device properties.
  5. Lee Ken K. ; Han Ke ; Srinivasan Lakshman ; Worster Bruce W., Method for characterizing defects on semiconductor wafers.
  6. Friedman J. David (Berkeley Heights NJ) Hansen Mark H. (Oakland CA) Hoyer James R. (Orlando FL) Nair Vijayan N. (Murray Hill NJ), Method for characterizing failed circuits on semiconductor wafers.
  7. Yoshida Toru (Yomato JPX) Sakaguchi Suguru (Chigasaki JPX) Kaneda Aizo (Shimodate JPX) Serizawa Kooji (Fujisawa JPX) Kishimoto Munehisa (Kamakura JPX) Mutoh Masaaki (Yokohama JPX) Matsumoto Kunio (Yo, Method for manufacturing a semiconductor device including wafer aging, probe inspection, and feeding back the results of.
  8. Saxena Kripa C. (San Jose CA), Method of investigating mammograms for masses and calcifications, and apparatus for practicing such method.
  9. Bacchi Paul E. (Novato CA) Filipski Paul S. (Greenbrae CA), Noncentering specimen prealigner having improved specimen edge detection and tracking.
  10. Sato Mitsuya (Yokohama JPX) Hamasaki Bunei (Yokohama JPX), Wafer prober.
  11. Sato Mitsuya (Yokohama JPX) Ukaji Takao (Yokohama JPX) Yamaguchi Nobuhito (Yokohama JPX) Ohmori Taro (Yokohama JPX) Murakami Eiichi (Yokohama JPX), Wafer prober.

이 특허를 인용한 특허 (53)

  1. Fukuda,Isao; Akiyama,Shuji, Automatic guided vehicle, automatic guided vehicle system and wafer carrying method.
  2. Jin,Ju; Sadam,Satish; Verma,Vishal; Huang,Zhiyan; Lin,Siming; Robbins,Michael D; Forderhase,Paul F., Automatic wafer edge inspection and review system.
  3. Jensen, Earl; Kirk, Christopher, Defect inspection apparatus, system, and method.
  4. Rumsey,Brad D., Descriptor for identifying a defective die site.
  5. Rumsey, Brad D., Descriptor for identifying a defective die site and methods of formation.
  6. Fujiwara, Susumu, Die bonder for die-bonding a semiconductor chip to lead frame and method of producing a semiconductor device using the die bonder.
  7. Kim, Sang-Geun; Ahn, Seung-Chul, Die bonding equipment.
  8. Sang-Geun Kim KR; Seung-Chui Ahn KR, Die bonding method for manufacturing fine pitch ball grid array packages.
  9. Zhong,Wei Min; Yang,Yang; Loh,Choo Han; Chau,Keung, Die sorting apparatus and method.
  10. Lo, Chia-Chi; Yang, Cheng-Hsiung Yang; Hsu, Jun-Chung, Final defect inspection system.
  11. Ujihara,Takashi; Inomata,Hirotoshi; Fujita,Isao, Inspection method and inspection system of surface of article.
  12. Fuentes, Ruben; Dunlap, Brett, Integrated passive device structure and method.
  13. Jose R. Gonzalez-Martin ; Chris Karlsrud ; Robert Allen ; Toby Jordan ; Craig Howard ; Arthur Hamer ; Jeff Cunnane ; Periya Gopalan ; Bill Thornton ; Jon MacErnie ; Fernando Calderon, Mapping system for semiconductor wafer cassettes.
  14. Hasan,Talat Fatima, Measurement system cluster.
  15. Hasan,Talat Fatima, Measurement system cluster.
  16. Huemoeller, Ronald Patrick; Rusli, Sukianto; Darveaux, Robert F., Metal etch stop fabrication method and structure.
  17. Nadabar, Sateesha; Gerst, III, Carl W., Method and apparatus for industrial identification mark verification.
  18. Brad D. Rumsey, Method and apparatus for marking and identifying a defective die site.
  19. Kinney Patrick D. ; Uritsky Yuri ; Rao Nagaraja, Method and apparatus for selectively marking a semiconductor wafer.
  20. Olson, Tim; Foltz, Lisa, Method and apparatus for sorting semiconductor devices.
  21. Nadabar, Sateesha; Gopalakrishnan, Venkat K.; Gerst, III, Carl W., Method and apparatus for verifying two dimensional mark quality.
  22. Hunter,Reginald, Method and apparatus to provide for automated process verification and hierarchical substrate examination.
  23. Takagi, Yuji; Doi, Hideaki; Ono, Makoto, Method and system for manufacturing semiconductor devices, and method and system for inspecting semiconductor devices.
  24. Yuji Takagi JP; Hideaki Doi JP; Makoto Ono JP, Method and system for manufacturing semiconductor devices, and method and system for inspecting semiconductor devices.
  25. Rumsey,Brad D., Method for identifying a defective die site.
  26. Tigelaar Howard L. ; Guldi Richard L., Method for improving wafer sleuth capability by adding wafer rotation tracking.
  27. Farnworth, Warren M.; Gochnour, Derek J., Method for substrate mapping.
  28. Lo, Chia-Chi; Yang, Cheng-Hsiung; Hsu, Jun-Chung, Method of final defect inspection.
  29. Nagaswami Venkat R.,NLX ; Van Gessel Johannes G.,NLX ; Van Wezep Dries A.,NLX, Method of manufacturing integrated circuits.
  30. Gerst, III, Carl W.; Testa, Justin, Mobile hand held machine vision method and apparatus using data from multiple images to perform processes.
  31. Stubblefield, Todd D.; Gharis, Eugene T.; Reeves, George W., Multiprobe blob test in lieu of 100% probe test.
  32. Steffan Paul J. ; Yu Allen S., Non-defect image and data transfer and storage methodology.
  33. Phan Khoi A. ; Matt Bernard ; Maccrae Nicholas R., Parallel inspection of semiconductor wafers by a plurality of different inspection stations to maximize throughput.
  34. Tuttle, Ralph C.; Plunket, Christopher Sean; Slater, Jr., David B.; Negley, Gerald H.; Schneider, Thomas P., Pattern for improved visual inspection of semiconductor devices.
  35. Tuttle,Ralph C.; Plunket,Christopher Sean; Slater, Jr.,David B.; Negley,Gerald H.; Schneider,Thomas P., Pattern for improved visual inspection of semiconductor devices.
  36. Satake,Nobuo, Semiconductor device fabrication method.
  37. Kokta,Milan; Stone Sundberg,Jennifer; Cooke,Jeffrey; Ackerman,Ronald; Ong,Hung; Corrigan,Emily, Spinel articles and methods for forming same.
  38. Stone Sundberg,Jennifer; Kokta,Milan; Cink,Robert; Ong,Hung, Spinel boules, wafers, and methods for fabricating same.
  39. Farnworth, Warren M.; Gochnour, Derek J., Substrate mapping.
  40. Farnworth, Warren M.; Gochnour, Derek J., Substrate mapping.
  41. Farnworth, Warren M.; Gochnour, Derek J., Substrate mapping.
  42. Farnworth,Warren M.; Gochnour,Derek J., Substrate mapping.
  43. Alexander, Emily H.; Welch, Jerimiah G., System and method for acquiring images of medication preparations.
  44. Hasan,Talat Fatima, Systems and methods for metrology recipe and model generation.
  45. Boyle,Timothy J.; Richter,Wayne E.; Johnson,Ladd T.; Tom,Lawrence A., Testing circuits on substrate.
  46. Boyle,Timothy J.; Richter,Wayne E.; Johnson,Ladd T.; Tom,Lawrence A., Testing circuits on substrate.
  47. Boyle, Timothy J.; Richter, Wayne E.; Johnson, Ladd T.; Tom, Lawrence A., Testing circuits on substrates.
  48. Boyle, Timothy J.; Richter, Wayne E.; Johnson, Ladd T.; Tom, Lawrence A., Testing circuits on substrates.
  49. Boyle,Timothy J.; Richter,Wayne E.; Johnson,Ladd T.; Tom,Lawrence A., Testing circuits on substrates.
  50. Boyle,Timothy J.; Richter,Wayne E.; Johnson,Ladd T.; Tom,Lawrence A., Testing circuits on substrates.
  51. Boyle,Timothy J.; Richter,Wayne E.; Johnson,Ladd T.; Tom,Lawrence A., Testing circuits on substrates.
  52. William R. Johanson ; Craig Stevens ; Steve Kleinke ; Damon Genetti, Wafer centering system and method.
  53. Conboy, Michael R.; Allen, Jr., Sam H.; Coss, Jr., Elfido, Wafer rotation randomization for process defect detection in semiconductor fabrication.
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