초록 ▼

To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensi

To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

대표청구항 ▼

[ What is claimed is:] [1.] A method of manufacturing a semiconductor integrated circuit, comprising the steps of:forming a plurality of transistors on a surface of a semiconductor region of a silicon wafer, metal-interconnecting electrodes of said transistors;forming a protecting film on said metal

[ What is claimed is:] [1.] A method of manufacturing a semiconductor integrated circuit, comprising the steps of:forming a plurality of transistors on a surface of a semiconductor region of a silicon wafer, metal-interconnecting electrodes of said transistors;forming a protecting film on said metal interconnection;first cutting said wafer along a scribed region of said wafer deeper than a depth of a diffusion layer of impurities; andsecond cutting said wafer along the scribed region of said wafer which was cut during the first cutting, characterized in that a cutting speed in said first cutting step is less than that in said second cutting step.