$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-019/00
출원번호 US-0686620 (1996-07-19)
발명자 / 주소
  • Trimberger Stephen M.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Haynes
인용정보 피인용 횟수 : 82  인용 특허 : 7

초록

A flash reconfigurable programmable logic device is applied as a dynamic execution unit for a sequence of instructions. The sequence of instructions includes control portion, and a portion which indicates which configuration of the flash configurable programmable logic device is to be used with that

대표청구항

[ What is claimed is:] [1.] A data processing system, comprising:a programmable logic device including configurable logic elements, a configuration store, and configuration select logic all located within the programmable logic device, the configuration store storing a set of configuration words def

이 특허에 인용된 특허 (7)

  1. Miyashita Takumi (Inagi JPX), Computer system having subinstruction surveillance capability.
  2. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  3. Tanagawa Kouji (Tokyo JPX), Instruction decoder simplification by reuse of bits to produce the same control states for different instructions.
  4. Maier Robert M. (San Jose CA) Zmyslowski Allan J. (Sunnyvale CA) Schober Carolee N. (Cupertino CA), Method for executing machine language instructions.
  5. Skruhak Robert J. (Austin TX) Gladden Michael E. (Austin TX), Microprogrammed data processor which includes a microsequencer in which a next microaddress output of a microROM is conn.
  6. Gingell Michael J. (Raleigh NC), System for controlling multiple line cards on a TDM bus.
  7. Buerkle Daniel J. (Newark Valley NY) Ngai Agnes Y. (Endwell NY), System for executing microinstruction routines by using hardware to calculate initialization parameters required therefo.

이 특허를 인용한 특허 (82)

  1. Knowles, Simon, Apparatus and method for configurable processing.
  2. Knowles, Simon, Apparatus and method for configurable processing.
  3. Ben David,Shay; Derby,Jeffrey Haskell; Fox,Thomas W.; Neeser,Fredy Daniel; Moreno,Jamie H.; Shvadron,Uzi; Zaks,Ayal, Apparatus and method for updating pointers for indirect and parallel register access.
  4. Kaptanoglu, Sinan; Mendel, David W., Apparatus and methods for time-multiplex field-programmable gate arrays.
  5. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
  6. Vorbach, Martin, Chip including memory element storing higher level memory data on a page by page basis.
  7. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
  8. De Oliveira Kastrup Pereira, Bernardo; Hoogerbrugge, Jan, Configurable data processing device with bit reordering on inputs and outputs of configurable logic function blocks.
  9. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  10. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  11. Mirsky,Ethan; French,Robert; Eslick,Ian, Controlling multiple context processing elements based on transmitted message containing configuration data, address mask, and destination indentification.
  12. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  13. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  14. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  15. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  16. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  17. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing system having integrated pipelined array data processor.
  18. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
  19. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
  20. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
  21. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  22. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  23. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
  24. Mirsky, Ethan; French, Robert; Eslick, Ian, Local control of multiple context processing elements with configuration contexts.
  25. Mirsky, Ethan; French, Robert; Eslick, Ian, Local control of multiple context processing elements with major contexts and minor contexts.
  26. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  27. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  28. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  29. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  30. Khandekar Narendra N. ; Clohset Steven, Method and apparatus for communicating a configuration sequence throughout an integrated circuit chip.
  31. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  32. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  33. Vorbach, Martin, Method for debugging reconfigurable architectures.
  34. Vorbach, Martin, Method for debugging reconfigurable architectures.
  35. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  36. Vorbach,Martin, Method for debugging reconfigurable architectures.
  37. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
  38. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  39. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
  40. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
  41. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  42. May,Frank; N?ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
  43. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Method of processing data with an array of data processors according to application ID.
  44. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  45. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  46. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  47. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  48. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
  49. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
  50. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  51. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  52. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  53. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
  54. Vorbach, Martin, Methods and devices for treating and/or processing data.
  55. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.
  56. Vorbach, Martin, Multi-processor with selectively interconnected memory units.
  57. Vorbach, Martin, Multiprocessor having associated RAM units.
  58. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.
  59. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
  60. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  61. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  62. Vorbach,Martin; M체nch,Robert, Process for automatic dynamic reloading of data flow processors (DFPS) and units with two-or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like).
  63. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  64. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  65. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  66. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  67. Inuo, Takeshi, Reconfigurable electric computer, semiconductor integrated circuit and control method, program generation method, and program for creating a logic circuit from an application program.
  68. Vorbach, Martin, Reconfigurable elements.
  69. Vorbach, Martin, Reconfigurable elements.
  70. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
  71. Vorbach,Martin; M?nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
  72. Nickolls, John R.; Johnson, Scott D.; Williams, Mark; Mirsky, Ethan; Kirthiranjan, Kambdur; Pant, Amrit Raj; Madar, III, Lawrence J., Reconfigurable processing system and method.
  73. Vorbach, Martin, Reconfigurable sequencer structure.
  74. Vorbach, Martin, Reconfigurable sequencer structure.
  75. Vorbach, Martin, Reconfigurable sequencer structure.
  76. Vorbach, Martin, Reconfigurable sequencer structure.
  77. Vorbach,Martin, Reconfigurable sequencer structure.
  78. Vorbach, Martin; Bretz, Daniel, Router.
  79. Vorbach,Martin; Bretz,Daniel, Router.
  80. Vorbach,Martin; M?nch,Robert, Run-time reconfiguration method for programmable units.
  81. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
  82. Kulakowski, Robert T.; Mautner, Craig; Fahy, James B.; Bronte, Jeffrey; Hutchins, Greg, System and method for defining programmable processing steps applied when protecting the data.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로