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Reconfigurable computing architecture for providing pipelined data paths

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
출원번호 US-0897094 (1997-07-18)
발명자 / 주소
  • Ebeling William Henry Carl
  • Cronquist Darren Charles
  • Franklin Paul David
출원인 / 주소
  • University of Washington
대리인 / 주소
    Christensen O'Connor Johnson & Kindness PLLC
인용정보 피인용 횟수 : 235  인용 특허 : 10

초록

A configurable computing architecture (10) has its functionality controlled by a combination of static and dynamic control, wherein the configuration is referred to as static control and instructions are referred to as dynamic control. A reconfigurable data path (12) has a plurality of elements incl

대표청구항

[ The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:] [49.] A method of mapping a computational application to a reconfigurable computing architecture for executing a plurality of applications, each application being executed over a plural

이 특허에 인용된 특허 (10)

  1. Dapp Michael C. (Endwell NY) Barker Thomas N. (Vestal NY) Dieffenderfer James W. (Owego NY) Knowles Billy J. (Kingston NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Rolfe David , Advanced parallel processor including advanced support hardware.
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  9. Kung Hsiang-Tsung (Pittsburgh PA) Leiserson Charles E. (Pittsburgh PA), Systolic array apparatuses for matrix computations.
  10. Khan Emdadur R. (San Jose CA), Systolic array for multidimensional matrix computations.

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  184. Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew J., Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch.
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  188. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.
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  214. Vorbach, Martin; Bretz, Daniel, Router.
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  219. Kalkunte,Suresh S.; Hooper,Donald F., Scheduling system for transmission of cells to ATM virtual circuits and DSL ports.
  220. Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew, Scratchpad memory.
  221. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas, Secure storage of program code for an embedded system.
  222. Gouldey,Brent I.; Fuster,Joel J.; Rapp,John; Jones,Mark, Service layer architecture for memory access system and method.
  223. Rosenbluth, Mark B.; Wolrich, Gilbert; Bernstein, Debra, Software controlled content addressable memory in a general purpose execution datapath.
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  225. Adiletta,Matthew J.; Wheeler,William; Redfield,James; Cutter,Daniel; Wolrich,Gilbert, Sram controller for parallel processor architecture including a read queue and an order queue for handling requests.
  226. Master,Paul L.; Watson,John, Storage and delivery of device features.
  227. Cronquist,Darren C.; Schlansker,Michael S., System and method for creating systolic solvers.
  228. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.
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  230. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  231. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  232. Vail, David Kenyon; Tabor, Frank J.; Blom, Daniel P.; Wilson, Stephen S., Temperature sensor and related methods.
  233. Wolrich,Gilbert; Bernstein,Debra; Hooper,Donald; Adiletta,Matthew J.; Wheeler,William, Thread signaling in multi-threaded processor.
  234. Dante, Conrad; Rutledge, David Lee; Wicker, Jr., David J., Vector routing in a programmable logic device.
  235. Rosenbluth,Mark B.; Bernstein,Debra; Wolrich,Gilbert, Write queue descriptor count instruction for high speed queuing.
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