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A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second proces

A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

대표청구항 ▼

[ We claim:] [7.] A microprocessor, comprising:a reduced instruction set computer (RISC) core for executing a RISC instruction, a very long instruction word (VLIW) table for storing VLIW instructions, a VLIW core for executing a VLIW instruction, and a VLIW start decision unit for controlling operat

[ We claim:] [7.] A microprocessor, comprising:a reduced instruction set computer (RISC) core for executing a RISC instruction, a very long instruction word (VLIW) table for storing VLIW instructions, a VLIW core for executing a VLIW instruction, and a VLIW start decision unit for controlling operation switching between said RISC core and said VLIW core,wherein when said RISC core executes a subroutine call or a branch instruction out of RISC instructions, a VLIW instruction is read from said VLIW table by use of a branch destination address, operation is transferred by said VLIW start decision unit from said RISC core to said VLIW core, and said VLIW core is caused to operate until a VLIW instruction completion code is read from said VLIW table; anda circuit for examining whether an operation of the VLIW instruction executed subsequent to a branch to the VLIW instruction is relevant to an operation of the RISC instruction which is restored after the execution of the VLIW instruction, said microprocessor being capable of executing the RISC instruction at the restoring destination in parallel without waiting for the completion of the VLIW instruction when no relevance exists.