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Method for making high-Q inductive elements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/764
출원번호 US-0069346 (1998-04-29)
발명자 / 주소
  • Farrar Paul A.
  • Forbes Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 71  인용 특허 : 13

초록 ▼

A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor through the via ho

대표청구항 ▼

[ We claim:] [1.] A method of forming an air bridge on a substrate, comprising the sequential steps of:forming a first oxide insulator on a base layer;forming a first conductor on the first oxide insulator;patterning the first conductor;forming a second oxide insulator over the first insulator;formi

이 특허에 인용된 특허 (13)

  1. Lee Kyu-Woong (Arlington MA) Durschlag Mark S. (Natick MA) Day John (Lexington MA), Evaporated thick metal and airbridge interconnects and method of manufacture.
    상세보기
  2. Prasad Jayasimha S. (Tigard OR) Park Song W. (Aloha OR) Vetanen William A. (Sherwood OR) Beers Irene G. (Sherwood OR) Haynes Curtis M. (Portland OR), Implant-free heterojunction bioplar transistor integrated circuit process.
    상세보기
  3. Klatskin Jerome Barnard (Princeton Junction NJ) Rosen Arye (Cherry Hill NJ), Method of electrically interconnecting semiconductor elements.
    상세보기
  4. Tam Gordon (Chandler AZ) Granick Lisa R. (Philadelphia PA), Method of fabricating airbridge metal interconnects.
    상세보기
  5. Chen Fusen E. (Dallas TX) Liou Fu-Tai (Carrollton TX) Dixit Girish A. (Dallas TX), Method of forming vias.
    상세보기
  6. Chino Toyoji (Osaka JPX) Matsuda Kenichi (Osaka JPX) Shibata Jun (Osaka JPX), Method of making semiconductor device with air-bridge interconnection.
    상세보기
  7. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
    상세보기
  8. Nakano Hirofumi (Itami JPX), Multi-layer wiring.
    상세보기
  9. Miura Takao,JPX ; Yamauchi Tunenori,JPX ; Monma Yoshinobu,JPX ; Goto Hiroshi,JPX, Process for manufacturing semiconductor devices separated by an air-bridge.
    상세보기
  10. Gardner Donald S., Process of fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circu.
    상세보기
  11. Klose Helmut,DEX ; Weber Werner,DEX ; Bertagnolli Emmerich,DEX ; Koppe Siegmar,DEX ; Hubner Holger,DEX, Semiconductor component for vertical integration and manufacturing method.
    상세보기
  12. Ohya Shuichi,JPX ; Sakao Masato,JPX ; Takaishi Yoshihiro,JPX ; Kajiyana Kiyonori,JPX ; Akimoto Takeshi,JPX ; Oguro Shizuo,JPX ; Shishiguchi Seiichi,JPX, Semiconductor memory device having trench isolation regions and bit lines formed thereover.
    상세보기
  13. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
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  1. Farrar, Paul A.; Geusic, Joseph E., Aligned buried structures formed by surface transformation of empty spaces in solid state materials.
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  2. Farrar, Paul A.; Geusic, Joseph E., Alignment for buried structures formed by surface transformation of empty spaces in solid state materials.
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  3. Farrar, Paul A., Aluminum-beryllium alloys for air bridges.
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  4. Farrar, Paul A., Aluminum-beryllium alloys for air bridges.
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  5. Farrar, Paul A., Aluminum-beryllium alloys for air bridges.
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  6. Ahn, Kie Y.; Forbes, Leonard, Bipolar transistors with low-resistance emitter contacts.
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  7. Ahn, Kie Y.; Forbes, Leonard, Bipolar transistors with low-resistance emitter contacts.
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  8. Ahn,Kie Y.; Forbes,Leonard, Bipolar transistors with low-resistance emitter contacts.
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  9. Farrar, Paul A.; Noble, Wendell P., Buried conductors.
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  10. Leonard Forbes, CMOS linear amplifier formed with nonlinear transistors.
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  11. Forbes, Leonard, CMOS voltage controlled phase shift oscillator.
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  12. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
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  13. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
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  14. Zuo, Chengjie; Kim, Daeik Daniel; Berdy, David Francis; Yun, Changhan Hobie; Lan, Je-Hsiung Jeffrey; Mikulka, Robert Paul; Velez, Mario Francisco; Kim, Jonghae; Nowak, Matthew Michael; Spring, Ryan Scott C.; Zhang, Xiangdong, Frequency multiplexer.
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  15. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  16. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  17. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
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  18. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
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  19. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
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  20. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
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  21. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
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  22. Noble, Wendell P.; Forbes, Leonard, Highly conductive composite polysilicon gate for CMOS integrated circuits.
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  23. Wendell P. Noble ; Leonard Forbes, Highly conductive composite polysilicon gate for CMOS integrated circuits.
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  24. Lo, Chi Shun; Lan, Je-Hsiung; Velez, Mario Francisco; Kim, Jonghae, Hybrid transformer structure on semiconductor devices.
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  25. Norstrom, Hans; Bjormander, Carl; Johansson, Ted, Integrated circuit inductor structure and non-destructive etch depth measurement.
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  26. Lan, Je-Hsiung; Lo, Chi Shun; Kim, Jonghae; Velez, Mario Francisco; Hong, John H., Integration of a replica circuit and a transformer above a dielectric substrate.
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  27. Lan, Je-Hsiung; Lo, Chi Shun; Kim, Jonghae; Velez, Mario Francisco; Hong, John H., Integration of a replica circuit and a transformer above a dielectric substrate.
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  28. Forbes,Leonard, Method and apparatus for providing clock signals at different locations with minimal clock skew.
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  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
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  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
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  31. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
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  32. Farrar, Paul A.; Geusic, Joseph E., Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials.
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  33. Farrar, Paul A.; Geusic, Joseph E., Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials.
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  34. Chen Wei-Fan,TWX, Method of fabricating on-chip inductor.
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  35. Farrar, Paul A.; Noble, Wendell P., Method of forming buried conductors.
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  36. Chu Jerome Tsu-Rong, Method of manufacturing lateral high-Q inductor for semiconductor devices.
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  37. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  38. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  40. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  42. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
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  43. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
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  44. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
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  45. Forbes Leonard ; Farrar Paul A. ; Ahn Kie Y., Methods and structures for gold interconnections in integrated circuits.
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  46. Ahn, Kie Y.; Forbes, Leonard; Farrar, Paul A., Methods and structures for metal interconnections in integrated circuits.
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  47. Ahn,Kie Y.; Forbes,Leonard; Farrar,Paul A., Methods and structures for metal interconnections in integrated circuits.
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  48. Forbes, Leonard; Farrar, Paul A.; Ahn, Kie Y., Methods and structures for silver interconnections in integrated circuits.
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  49. Parks, Jay S., Microelectronic die including low RC under-layer interconnects.
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  50. Parks, Jay S., Microelectronic die including low RC under-layer interconnects.
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  51. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
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  53. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
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  59. Ahn,Kie Y.; Forbes,Leonard, Semiconductor device with electrically coupled spiral inductors.
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  60. Ahn,Kie Y; Forbes,Leonard, Semiconductor device with electrically coupled spiral inductors.
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  61. Farrar, Paul A., Structures and methods to enhance copper metallization.
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  62. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  63. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  69. Kim, Daeik Daniel; Zuo, Chengjie; Yun, Changhan Hobie; Velez, Mario Francisco; Mikulka, Robert Paul; Zhang, Xiangdong; Kim, Jonghae; Lan, Je-Hsiung, Varying thickness inductor.
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  70. Lan, Je-Hsiung; Lo, Chi Shun; Kim, Jonghae; Hong, John H., Vertical-coupling transformer with an air-gap structure.
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  71. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
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