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Crack stops 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/544
출원번호 US-0061538 (1998-04-16)
발명자 / 주소
  • Mitwalsky Alexander R.
  • Chen Tze-Chiang
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Braden
인용정보 피인용 횟수 : 41  인용 특허 : 5

초록

Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The di

대표청구항

[ What is claimed is:] [1.] A semiconductor wafer comprising a substrate for fabricating integrated circuits, comprising:a dicing channel disposed between adjacent ones of said integrated circuits;such dicing channel having steps disposed in underling surface portions of the substrate along a periph

이 특허에 인용된 특허 (5)

  1. Richardson William E. (Rutland MA), Method for making IC die with dielectric isolation.
  2. Abe Masahiro (Yokohama JPX) Miyagawa Masafumi (Sagamihara JPX) Nakamura Hatsuo (Yokohama JPX) Yonezawa Toshio (Yokosuka JPX), Method of dicing a semiconductor wafer.
  3. Vokoun ; III Edward R. (Tijeras NM), Method of dicing semiconductor wafers which produces shards less than 10 microns in size.
  4. Cholewa Mark B. (Mt. Penn Township ; Berks County PA) Osenbach John W. (Kutztown PA) Segner Bryan P. (Piscataway NJ), Method of fabrication for electro-optical devices.
  5. Takagi Hiroshi (Hyogo JPX), Wafer having a dicing area having a step region covered with a conductive layer and method of manufacturing the same.

이 특허를 인용한 특허 (41)

  1. Prymak, John D., Capacitor comprising flex crack mitigation voids.
  2. Prymak, John D., Capacitor comprising flex crack mitigation voids.
  3. Goebel, Thomas; Kaltalioglu, Erdem; Kim, Sun-Oo, Capacitor integrated in a structure surrounding a die.
  4. Axel Christoph Brintzinger, Chip crack stop design for semiconductor chips.
  5. Mitwalsky Alexander R. ; Chen Tze-Chiang, Crack stops.
  6. Shaw, Thomas M; Lane, Michael W; Liu, Xio Hu; Bonilla, Griselda; Doyle, James P; Landis, Howard S; Liniger, Eric G, Crack trapping and arrest in thin film structures.
  7. Mieczkowski, Van Allen; Namishia, Daniel James, Devices with crack stops.
  8. Mieczkowski, Van Allen; Namishia, Daniel James, Devices with crack stops.
  9. Hung, Cheng-Chou; Liang, Victor-Chiang; Jao, Jui-Meng; Li, Cheng-Hung; Huang, Sheng-Yi; Li, Tzung-Lin; Zhang, Huai-Wen; Tseng, Chih-Yu, Die seal ring.
  10. Shaw,Thomas M; Lane,Michael W; Liu,Xio Hu; Bonilla,Griselda; Doyle,James P; Landis,Howard S; Liniger,Eric G, Method of forming crack trapping and arrest in thin film structures.
  11. Barth, Hans-Joachim; Tews, Helmut Horst, Methods of forming moisture barrier capacitors in semiconductor components.
  12. Barth, Hans-Joachim; Tews, Helmut Horst, Moisture barrier capacitors in semiconductor components.
  13. Barth, Hans-Joachim; Tews, Helmut Horst, Moisture barrier capacitors in semiconductor components.
  14. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  15. Chi-Fa Lin TW; Wei-Tsu Tseng TW; Min-Shinn Feng TW, Scribe line structure for preventing from damages thereof induced during fabrication.
  16. Farooq, Mukta G.; Griesemer, John A.; Landers, William F.; Melville, Ian D.; Shaw, Thomas M.; Zhu, Huilong, Structure and method for making crack stop for 3D integrated circuits.
  17. Farooq, Mukta G; Griesemer, John A; Landers, William F; Melville, Ian D; Shaw, Thomas M; Zhu, Huilong, Structure and method for making crack stop for 3D integrated circuits.
  18. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  19. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  20. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  27. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  28. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  29. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  30. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  31. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  32. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  33. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  34. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  35. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  36. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  37. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  38. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  39. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  40. Edelstein, Daniel C.; Gaynes, Michael A.; Shaw, Thomas M.; Webb, Bucknell C.; Yu, Roy R., Volumetric integrated circuit and volumetric integrated circuit manufacturing method.
  41. Min-Seok Ha KR; Jin-Kee Choi KR; Cheol Jeong KR, Wafer grooves for reducing semiconductor wafer warping.
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