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Programmable switch matrix and method of programming 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/173
출원번호 US-0772735 (1996-12-23)
발명자 / 주소
  • Gardner Robert M.
  • Hallmark Jerald A.
  • Marshall Daniel S.
  • Ooms William J.
출원인 / 주소
  • Motorola, Inc.
대리인 / 주소
    Dover
인용정보 피인용 횟수 : 38  인용 특허 : 7

초록

A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) f

대표청구항

[ We claim:] [1.] A programmable switch, comprising:a plurality of ferroelectric transistors arranged to provide a connecting conduction path between a first line, a second line, a third line, and a fourth line, wherein a signal on any line can be transferred through the connecting conduction path o

이 특허에 인용된 특허 (7)

  1. Ishihara Hiroshi (Tokyo JPX), Ferrelectric adaptive-learning type product-sum operation circuit element and circuit using such element.
  2. Freeman Ross H. (San Jose CA), Integrated circuit programmable cross-point connection technique.
  3. Takasu Hidemi (Kyoto JPX), Nonvolatile memory device having ferroelectric film.
  4. Ozawa Takanori (Ukyo JPX), Nonvolatile memory device utilizing field effect transistor having ferroelectric gate film.
  5. Duong Khue (San Jose CA) Trimberger Stephen M. (San Jose CA) Mehrotra Alok (Los Gatos CA), Programmable single buffered six pass transistor configuration.
  6. Hoshiba Kazuhiro (Kyoto JPX), Semiconductor storage device with a ferroelectric transistor storage cell.
  7. Carter William S. (Santa Clara CA), Special interconnect for configurable logic array.

이 특허를 인용한 특허 (38)

  1. Kiel,Steven Lee; Krening,Douglas Norman; Lehman,Lark Edward; Schneiderwind,Michael Joseph, Dynamically configurable logic gate using a non-linear element.
  2. Myoungho Lim ; Vikram Joshi ; Jeffrey W. Bacon ; Joseph D. Cuchiaro ; Larry D. McMillan ; Carlos A. Paz de Araujo, Ferroelectric field effect transistor, memory utilizing same, and method of operating same.
  3. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor for storing two data bits.
  4. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor for storing two data bits.
  5. Dimmler,Klaus; Gnadinger,Alfred P., Ferroelectric transistor for storing two data bits.
  6. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor with enhanced data retention.
  7. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor with enhanced data retention.
  8. Myers, Brent A.; Fox, James G., High utilization universal logic array with variable circuit topology and logistic map circuit to realize a variety of logic gates with constant power signatures.
  9. Ditto, William L.; Murali, Krishnamurthy; Sinha, Sudeshna; Miliotis, Abraham, Logic based on the evolution of nonlinear dynamical systems.
  10. Ditto, William L.; Murali, Krishnamurthy; Sinha, Sudeshna; Miliotis, Abraham, Logic based on the evolution of nonlinear dynamical systems.
  11. Ditto, William L.; Murali, Krishnamurthy; Sinha, Sudeshna, Logic circuits having dynamically configurable logic gate arrays.
  12. Woodard,Stanley E.; Taylor,Bryant D., Magnetic field response measurement acquisition system.
  13. Woodard,Stanley E.; Taylor,Bryant D.; Shams,Qamar A.; Fox, legal representative,Christopher L.; Fox, legal representative,Melanie L.; Bryant,Robert G.; Fox, deceased,Robert L., Magnetic field response measurement acquisition system.
  14. Woodard, Stanley E.; Taylor, Bryant D., Magnetic field response sensor for conductive media.
  15. Woodard, Stanley E.; Taylor, Bryant Douglas, Magnetic field response sensor for conductive media.
  16. Woodard,Stanley E.; Taylor,Bryant D., Magnetic field response sensor for conductive media.
  17. Ditto,William L.; Murali,Krishnamurthy; Sinha,Sudeshna, Method and apparatus for a chaotic computing module.
  18. Ditto,William L.; Murali,Krishnamurthy; Sinha,Sudeshna, Method and apparatus for a chaotic computing module using threshold reference signal implementation.
  19. Woodard, Stanley E.; Taylor, Bryant D., Method of mapping anomalies in homogenous material.
  20. Ditto, William L.; Sinha, Sudeshna; Miliotis, Abraham, Non-linear dynamical search engine.
  21. Yoneda, Seiichi; Nishijima, Tatsuji, Programmable logic device.
  22. Yoneda, Seiichi; Nishijima, Tatsuji, Programmable logic device.
  23. Masui, Shoichi; Oura, Michiya; Ninomiya, Tsuzumi; Yokozeki, Wataru; Mukaida, Kenji, Programmable logic device with ferroelectric configuration memories.
  24. Myers, Brent Arnold; Fox, James Gregory, Protecting data from decryption from power signature analysis in secure applications.
  25. Myers, Brent Arnold; Fox, James Gregory, Protecting data from decryption from power signature analysis in secure applications.
  26. Campos Canton, Eric; Campos Canton, Isaac; Rosu, Haret Codratian, Reconfigurable dynamic logic gate with linear core.
  27. Bryant,John, Remotely reconfigurable system for mapping structure subsurface geological anomalies.
  28. Bryant, John, Remotely reconfigurable system for mapping subsurface geological anomalies.
  29. Bryant, John, Remotely reconfigurable system for mapping subsurface geological anomalies.
  30. Bryant, John; Willey, H. Michael; Lehmann, Guenter H.; Salamat, Arash Tom; Edgar, Michael; Leopold, Jerry, Remotely reconfigurable system for mapping subsurface geological anomalies.
  31. Bryant, John; Willey, H. Michael; Lehmann, Guenter H.; Salamat, Arash Tom; Edgar, Michael; Leopold, Jerry, Remotely reconfigurable system for mapping subsurface geological anomalies.
  32. Takasu Hidemi,JPX, Sequential circuits using ferroelectrics and semiconductor devices using the same.
  33. Gnadinger, Alfred P., Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric.
  34. Gnadinger,Fred P., Single transistor rare earth manganite ferroelectric nonvolatile memory cell.
  35. Nozawa, Hiroshi; Koyama, Shinzo; Fujimori, Yoshikazu, Switch matrix circuit, logical operation circuit, and switch circuit.
  36. Nozawa,Hiroshi; Koyama,Shinzo; Fujimori,Yoshikazu, Switch matrix circuit, logical operation circuit, and switch circuit.
  37. Hatcher, Ryan M.; Sengupta, Rwik; Bowen, Chris, Unipolar complementary logic.
  38. Woodard, Stanley E., Wireless open-circuit in-plane strain and displacement sensor requiring no electrical connections.
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