$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Process for forming a gate-quality insulating layer on a silicon carbide substrate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/78
출원번호 US-0760056 (1996-12-04)
발명자 / 주소
  • Wang Xiewen
출원인 / 주소
  • Yale University
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 53  인용 특허 : 7

초록

A method of fabricating a semiconductor structure involving the steps of providing a SiC substrate, treating the SiC substrate with an N.sub.2 O-containing plasma, and forming a dielectric layer on the surface of the pretreated SiC substrate. A semiconductor structure produced by the method above. A

대표청구항

[ What is claimed is:] [1.] A method of fabricating a semiconductor structure, said method comprising:providing a SiC substrate;pretreating the SiC substrate with a plasma generated in an atmosphere containing N.sub.2 O; andforming a dielectric layer on the surface of the pretreated SiC substrate, w

이 특허에 인용된 특허 (7)

  1. Ueno Katsunori,JPX ; Urushidani Tatsuo,JPX ; Hashimoto Koichi,JPX ; Ogino Shinji,JPX ; Seki Yasukazu,JPX, Manufacturing method of SiC Schottky diode.
  2. Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
  3. Suzuki Atsushi (Kanagawa JPX), Method for forming silicon oxide layer.
  4. Weitzel Charles E. ; Fisk Edward L. ; Pack Sung P., Method for planarizing wide bandgap semiconductor devices.
  5. Kamiyama Eiji (Saitama-ken JPX) Fusegawa Kazuhiro (Saitama-ken JPX) Toyama Nosho (Saitama-ken JPX), Method of producing a silicon carbide semiconductor device.
  6. Nakahigashi Takahiro (Kyoto JPX) Murakami Hiroshi (Kyoto JPX) Otani Satoshi (Osaka JPX) Tabata Takao (Kyoto JPX) Maeda Hiroshi (Kyoto JPX) Kirimura Hiroya (Kyoto JPX) Kuwahara Hajime (Kyoto JPX), Plasma-CVD method and apparatus.
  7. Ueno Katsunori (Nagano JPX), Silicon carbide trench MOSFET.

이 특허를 인용한 특허 (53)

  1. Allibert, Frédéric; Kerdiles, Sébastien, Composite substrate and method of fabricating the same.
  2. Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant; Palmour, John Williams; Allen, Scott, Edge termination structure employing recesses for edge termination elements.
  3. Ryu, Sei-Hyung; Capell, Doyle Craig; Cheng, Lin; Dhar, Sarit; Jonas, Charlotte; Agarwal, Anant; Palmour, John, Field effect transistor devices with low source resistance.
  4. Ryu, Sei-Hyung; Capell, Doyle Craig; Cheng, Lin; Dhar, Sarit; Jonas, Charlotte; Agarwal, Anant; Palmour, John, Field effect transistor devices with low source resistance.
  5. Dhar, Sarit; Ryu, Sei-Hyung; Agarwal, Anant; Williams, John Robert, Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions.
  6. Zhang, Qingchun, High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability.
  7. Das, Mrinal K.; Lin, Henry; Schupbach, Marcelo; Palmour, John Williams, High current, low switching loss SiC power module.
  8. Das, Mrinal K.; Lin, Henry; Schupbach, Marcelo; Palmour, John Williams, High current, low switching loss SiC power module.
  9. Das, Mrinal K.; Callanan, Robert J.; Lin, Henry; Palmour, John Williams, High performance power module.
  10. Zhang, Qingchun; Ryu, Sei-Hyung; Jonas, Charlotte; Agarwal, Anant K., High power insulated gate bipolar transistors.
  11. Zhang, Qingchun; Ryu, Sei-Hyung; Jonas, Charlotte; Agarwal, Anant K., High power insulated gate bipolar transistors.
  12. Ryu, Sei-Hyung; Zhang, Qingchun, High voltage insulated gate bipolar transistors with minority carrier diverter.
  13. Das, Mrinal Kanti; Lipkin, Lori A.; Palmour, John W.; Sheppard, Scott; Hagleitner, Helmut, High voltage, high temperature capacitor and interconnection structures.
  14. Zhang, Qingchun, Insulated gate bipolar transistors including current suppressing layers.
  15. Zhang, Qingchun, Insulated gate bipolar transistors including current suppressing layers.
  16. Zhang, Qingchun; Ryu, Sei-Hyung, Junction Barrier Schottky diodes with current surge capability.
  17. Huang, Judy; Bencher, Chris; Rathi, Sudha, Method and apparatus for reducing fixed charges in a semiconductor device.
  18. Lipkin, Lori A.; Das, Mrinal Kanti; Palmour, John W., Method of N2O growth of an oxide layer on a silicon carbide layer.
  19. Das,Mrinal Kanti; Lipkin,Lori A., Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment.
  20. Nakashima, Hiroshi; Yang, Haigui; Sumida, Hitoshi, Method of manufacturing semiconductor device.
  21. Shinji Amano JP; Eiichi Okuno JP; Tsuyoshi Yamamoto JP, Method of manufacturing silicon carbide semiconductor device having oxide film formed thereon with low on-resistances.
  22. Das,Mrinal Kanti; Lipkin,Lori A.; Palmour,John W.; Sheppard,Scott; Hagleitner,Helmut, Methods of fabricating high voltage, high temperature capacitor and interconnection structures.
  23. Das, Mrinal K.; Hull, Brett; Krishnaswami, Sumi, Methods of forming SiC MOSFETs with high inversion layer mobility.
  24. Das, Mrinal K.; Hull, Brett; Krishnaswami, Sumi, Methods of forming SiC MOSFETs with high inversion layer mobility.
  25. Hull, Brett Adam; Zhang, Qingchun, Methods of forming semiconductor devices including epitaxial layers and related structures.
  26. Das,Mrinal Kanti; Saxler,Adam William, Nitrogen passivation of interface states in SiO/SiC structures.
  27. Oborina, Elena I.; Hoff, Andrew, Noncontact determination of interface trap density for semiconductor-dielectric interface structures.
  28. Oborina, Elena I.; Hoff, Andrew, Noncontact determination of interface trap density for semiconductor-dielectric interface structures.
  29. Huang,Judy, Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers.
  30. Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant Kumar; Palmour, John Williams; Allen, Scott, Power module for supporting high current densities.
  31. Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant Kumar; Palmour, John Williams; Allen, Scott, Power module having a switch module for supporting high current densities.
  32. Zhang, Qingchun; Richmond, James Theodore; Agarwal, Anant K.; Ryu, Sei-Hyung, Power switching devices having controllable surge current capabilities.
  33. Ryu, Sei-Hyung; Agarwal, Anant; Das, Mrinal Kanti; Lipkin, Lori A.; Palmour, John W.; Singh, Ranbir, SILICON CARBIDE POWER METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING A SHORTING CHANNEL AND METHODS OF FABRICATING SILICON CARBIDE METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING.
  34. Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant Kumar; Palmour, John Williams; Allen, Scott, Schottky diode.
  35. Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant Kumar; Palmour, John Williams; Allen, Scott, Schottky diode.
  36. Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant; Palmour, John Williams; Allen, Scott, Schottky diode.
  37. Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant; Palmour, John Williams; Allen, Scott, Schottky diode employing recesses for elements of junction barrier array.
  38. Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant, Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same.
  39. Hull, Brett Adam; Zhang, Qingchun, Semiconductor devices including epitaxial layers and related methods.
  40. Zhang, Qingchun; Henning, Jason, Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same.
  41. Zhang, Qingchun, Semiconductor devices with heterojunction barrier regions and methods of fabricating same.
  42. Zhang, Qingchun, Semiconductor devices with heterojunction barrier regions and methods of fabricating same.
  43. Zhang, Qingchun, Semiconductor devices with heterojunction barrier regions and methods of fabricating same.
  44. Zhang, Qingchun, Semiconductor devices with heterojunction barrier regions and methods of fabricating same.
  45. Ryu, Sei-Hyung, Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same.
  46. Ryu,Sei Hyung, Silicon carbide power devices with self-aligned source and well regions.
  47. Ryu,Sei Hyung, Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same.
  48. Yamashita, Kenya; Kitabatake, Makoto; Kusumoto, Osamu; Takahashi, Kunimasa; Uchida, Masao; Miyanaga, Ryoko, Silicon carbide-oxide layered structure, production method thereof, and semiconductor device.
  49. Callanan, Robert J.; Ryu, Sei-Hyung; Zhang, Qingchun, Solid-state pinch off thyristor circuits.
  50. Ryu, Sei-Hyung, Vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors.
  51. Ryu,Sei Hyung, Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors.
  52. Zhang, Qingchun, Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices.
  53. Zhang, Qingchun; Richmond, James Theodore; Callanan, Robert J., Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로