초록 ▼

A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus util

A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

대표청구항 ▼

[ What is claimed is:] [1.] A computer system, comprising:a plurality of bus devices including one or more processors and one or more storage devices;a system controller;a bus architecture coupling said plurality of bus devices and said system controller;first means adaptable for transferring each a

[ What is claimed is:] [1.] A computer system, comprising:a plurality of bus devices including one or more processors and one or more storage devices;a system controller;a bus architecture coupling said plurality of bus devices and said system controller;first means adaptable for transferring each address and data bus request from said plurality of bus devices to said system controller as said each address and data bus request is generated by said plurality of bus devices;second means adaptable for transferring, from said system controller to said plurality of bus devices, responses to said each address and data bus request, and wherein at least one of said each address and data bus request is a speculative bus request; andmeans for issuing a bus grant to a non-speculative bus request before issuing a bus grant to said speculative bus request even though said speculative bus request was received by said system controller before said non-speculative bus request was received by said system controller.