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Electroless gold plating method for forming inductor structures

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0944498 (1997-10-06)
발명자 / 주소
  • Lee Chwan-Ying,TWX
  • Huang Tzuen-Hsi,TWX
출원인 / 주소
  • Industrial Technology Research Institute, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 104  인용 특허 : 10

초록

The present invention provides a method of manufacturing an inductor element 46 using an electroless Au plating solution. The invention has three embodiments for forming the inductor. In the first embodiment, a first insulating layer 30 is formed over a semiconductor structure 10 20. An adhesion lay

대표청구항

[ What is claimed is:] [5.] A method of fabrication an inductor element for a semiconductor device; comprising the steps of:a) forming a first insulating layer over a semiconductor structure;b) forming and patterning an adhesion layer composed of polysilicon over said first insulating layer;c) selec

이 특허에 인용된 특허 (10)

  1. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Electroless copper plating method for forming integrated circuit structures.
  2. Feldman Leonard C. (Berkeley Heights NJ) Higashi Gregg S. (Basking Ridge NJ) Mak Cecilia Y. (Bedminster NJ) Miller Barry (Murray Hill NJ), Fabrication of electronic devices by electroless plating of copper onto a metal silicide.
  3. Burghartz Joachim Norbert ; Edelstein Daniel Charles ; Jahnes Christopher Vincent ; Uzoh Cyprian Emeka, Integrated circuit inductor.
  4. Inaba Yoshiharu (Kodaira JA) Kawanobe Toru (Kodaira JA), Method for electroless plating gold directly on tungsten or molybdenum.
  5. Iwamoto Yasuhiko (Tokyo JPX), Method for forming a metal conductor in semiconductor device.
  6. Kosaki Katsuya (Itami JPX), Method for manufacturing semiconductor device contact.
  7. Inaba Takashi (Tokyo JPX), Method for manufacturing semiconductor device having a multilayer wiring structure.
  8. Dow Stephen (Chandler AZ) Maass Eric C. (Scottsdale AZ) Marlin Bill (Phoenix AZ), Method of making an electronic device having an integrated inductor.
  9. Bhagat Jayant K. (930 Andover Way Los Altos CA 94022), Miniature inductor for integrated circuits and devices.
  10. Yakura James P. (Colorado Springs CO) Cole Richard K. (Woodland Park CO) Von Thun Matthew S. (Colorado Springs CO) Hass Crystal J. (Colorado Springs CO) Allman Derryl D. J. (Colorado Springs CO), Structure and method for remotely measuring process data.

이 특허를 인용한 특허 (104)

  1. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  2. Lin,Mou Shiung, Chip structure with redistribution traces.
  3. Farrar Paul A., Copper metallurgy in integrated circuits.
  4. Farrar, Paul A., Copper metallurgy in integrated circuits.
  5. O'brien, Kevin; Akolkar, Rohan; Indukuri, Tejaswi; Fajardo, Arnel M., Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance.
  6. Gallagher, William J.; O'Sullivan, Eugene J.; Wang, Naigang, Electroless plated material formed directly on metal.
  7. Gallagher, William J.; O'Sullivan, Eugene J.; Wang, Naigang, Electroless plating of cobalt alloys for on chip inductors.
  8. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.
  9. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper and other metals.
  10. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
  11. Farrar, Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
  12. Yen, Hsiao-Tsung; Luo, Cheng-Wei; Kuo, Chin-Wei; Jeng, Min-Chie, Helical spiral inductor between stacking die.
  13. Heng-Ming Hsu TW; Shyh-Chyi Wong TW; Chaochieh Tsai TW; Ssu-Pin Ma TW; Chao-Cheng Chen TW; Liang-Kun Huang TW, High Q inductor with Cu damascene via/trench etching simultaneous module.
  14. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  15. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  16. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  17. Farrar,Paul A., Hplasma treatment.
  18. Shigenobu Maeda JP; Yasuo Yamaguchi JP; Yuuichi Hirano JP; Takashi Ipposhi JP; Takuji Matsumoto JP, Inductor with patterned ground shield.
  19. Farrar, Paul A., Integrated circuit and seed layers.
  20. Farrar,Paul A., Integrated circuit and seed layers.
  21. Farrar,Paul A., Integrated circuit and seed layers.
  22. Farrar Paul A., Integrated circuit with oxidation-resistant polymeric layer.
  23. Shim,Dong sik; Na,Kyung won; Choi,Sang on; Park,Hae seok; Hwang,Jun sik, Magnetic field detecting element and method for manufacturing the same.
  24. Na,Kyung won, Magnetic field sensing device and a fabricating method of the same.
  25. Na,Kyung won, Magnetic field sensing device and a fabricating method of the same.
  26. Linville, Eric S.; Kief, Mark T., Magnetic write device with a cladded write assist element.
  27. Farrar, Paul A., Mask on a polymer having an opening width less than that of the opening in the polymer.
  28. Chikama, Yoshimasa; Izumi, Yoshihiro, Metal interconnections and active matrix substrate using the same.
  29. Izumi, Yoshihiro; Chikama, Yoshimasa; Kawashima, Satoshi; Hashimoto, Takaharu, Metal line, method for fabricating the metal line, thin film transistor employing the metal line and display device.
  30. Janice H. Nickel ; Thomas C. Anthony, Method for fabricating cladding layer in top conductor.
  31. Albertini, Jean-Baptiste; Peuzin, Jean-Claude, Method for increasing the operating frequency of a magnetic circuit and corresponding magnetic circuit.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  33. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  34. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
  35. Chwan-Ying Lee TW; Tzuen-Hsi Huang TW, Method of electroless plating copper on nitride barrier.
  36. Lee, Chwan-Ying; Huang, Tzuen-Hsi, Method of electroless plating copper on nitride barrier.
  37. Edelstein, Daniel C.; Andricacos, Panayotis C.; Cotte, John M.; Deligianni, Hariklia; Magerlein, John H.; Petrarca, Kevin S.; Stein, Kenneth J.; Volant, Richard P., Method of fabricating a high Q factor integrated circuit inductor.
  38. F. Scott Johnson, Method of fabricating a miniaturized integrated circuit inductor and transformer fabrication.
  39. Marian N. Webster NL, Method of manufacturing a semiconductor device comprising a semiconductor body having a surface provided with a coil having a magnetic core.
  40. Tsai Chao-chieh,TWX, Method to form a high Q inductor.
  41. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  42. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  43. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  44. Ahn,Kie Y.; Forbes,Leonard, Methods for making copper and other metal interconnections in integrated circuits.
  45. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  46. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  47. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  48. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
  49. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  50. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  51. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  52. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  53. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  54. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  55. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  56. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  57. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  58. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  59. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  60. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  61. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  62. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  63. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  64. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  65. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  66. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  67. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  68. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  69. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  70. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  71. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  72. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  73. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  74. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  75. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  76. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  77. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  78. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  79. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  80. Cha, Hye Yeon; Kweon, Young Do; Yoo, Young Seuck; Lee, Hwan Soo; Choi, Woon Chul, Power inductor and manufacturing method thereof.
  81. Tran, Dean; Akbany, Salim; DePace, Ronald A.; Jones, William L.; Johnson, Roosevelt, Precious alloyed metal solder plating process.
  82. Girardie, Lionel; David, Jean-Baptiste, Process for fabricating an electronic component incorporating an inductive microcomponent.
  83. Tanabe, Hiroyuki; Kanagawa, Hitoki, Producing method of suspension board with circuit.
  84. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
  85. Davies,Robert B., Semiconductor device with inductive component and method of making.
  86. Davies,Robert B., Semiconductor device with inductive component and method of making.
  87. Farrar, Paul A., Structures and methods to enhance copper metallization.
  88. Farrar, Paul A., Structures and methods to enhance copper metallization.
  89. Farrar, Paul A., Structures and methods to enhance copper metallization.
  90. Farrar,Paul A., Structures and methods to enhance copper metallization.
  91. Farrar,Paul A., Structures and methods to enhance copper metallization.
  92. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  93. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  94. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  95. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  96. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  97. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  98. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  99. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  100. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  101. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
  102. Pust, Ladislav R.; Linville, Eric S., Wire-assisted magnetic write device with a gapped trailing shield.
  103. Gao, Kaizhong; Mao, Sining; Linville, Eric S.; Feng, Xuebing; Li, Shaoping; Bozeman, Steven Paul, Wire-assisted magnetic write device with low power consumption.
  104. Ionescu, Stefan A.; Pust, Ladislav R.; Johnson, Michael T.; Amin, Nurul, Wire-assisted magnetic write device with phase shifted current.
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