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A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas fo

A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.

대표청구항 ▼

[ What is claimed is:] [11.] A package-free boding pad structure, comprising:a substrate;a plurality of conductive layers above the substrate; anda plurality of insulation layers above the substrate, wherein adjacent conductive layers are separated from each other by an insulating layer, a plurality

[ What is claimed is:] [11.] A package-free boding pad structure, comprising:a substrate;a plurality of conductive layers above the substrate; anda plurality of insulation layers above the substrate, wherein adjacent conductive layers are separated from each other by an insulating layer, a plurality of bonding pad areas are formed on one of the conductive layers, each of the conductive layers and each of the insulation layers has a corresponding pattern so that at least no conductive layers are formed over the bonding pad areas, a plurality of open cavities that expose a portion of the bonding pad are formed inside the insulation layers above the bonding pad areas, and furthermore a diameter of the open cavity gets smaller on approaching the upper surface of uppermost insulation layer while the diameter gets bigger on approaching the conductive layer in the bonding pad area.