초록 ▼

A method is provided for the fabrication of fuses within a semiconductor IC structure, which fuses are delectable by a laser pulse or a low voltage electrical pulse typically below 3.5 V to reroute the electrical circuitry of the structure to remove a faulty element. The fuses are formed on the surf

A method is provided for the fabrication of fuses within a semiconductor IC structure, which fuses are delectable by a laser pulse or a low voltage electrical pulse typically below 3.5 V to reroute the electrical circuitry of the structure to remove a faulty element. The fuses are formed on the surface of circuitry which is coplanar with a surrounding dielectric such as the circuitry formed by a Damascene method. A preferred fuse material is silicon-chrome-oxygen and the preferred circuitry is copper.

대표청구항 ▼

[ We claim:] [1.] A method for forming at least one fuse, delectable by low voltage electrical pulses or by laser pulses for the purpose of rerouting various components on an integrated circuit, the fuse being formed on a planarized surface of exposed interconnection circuitry lines and surrounding

[ We claim:] [1.] A method for forming at least one fuse, delectable by low voltage electrical pulses or by laser pulses for the purpose of rerouting various components on an integrated circuit, the fuse being formed on a planarized surface of exposed interconnection circuitry lines and surrounding internal insulation, the method comprising the steps of:forming a planarized surface comprising the circuitry lines and surrounding internal insulation;depositing a thin layer of a fuse material on the planarized surface;defining the size and shape of the fuses and the circuitry lines connected by the fuses using a photolithographic photoresist material;exposing the photoresist;developing the exposed photoresist;etching the exposed layer of fuse material;stripping the remaining photolithographic photoresist material;depositing at least one layer of final insulating and passivating material on the fuses defined planarized surface;forming, by a damascene method, at least two via studs with each stud contacting the circuitry lines linked by the fuse; andforming metal pads on the upper surface of the final insulating and passivating layer contacting the via studs.