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Multiple loadlock system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/31
  • H01L-021/469
출원번호 US-0901485 (1997-07-28)
발명자 / 주소
  • Heyder Roger V.
  • Brezocsky Thomas B.
  • Davenport Robert E.
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Konrad, Raynes & Victor
인용정보 피인용 횟수 : 23  인용 특허 : 27

초록

A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe

대표청구항

[ What is claimed is:] [1.] A method of processing semiconductor workpieces, comprising:loading processed workpieces from a stack for workpieces in an evacuated holding chamber into a first cassette in an evacuated first chamber;unloading unprocessed workpieces from a second cassette in an evacuated

이 특허에 인용된 특허 (27)

  1. Hazano Shigeki (Yokohama CA JPX) Shibagaki Masahiro (San Jose CA) Jyo Hidetaka (Sagamihara JPX) Sensui Reiichiro (Sagamihara JPX) Iwami Munenori (Yokohama JPX) Suzuki Noboru (Chigasaki JPX), Apparatus for producing semiconductor devices.
  2. Beaver ; II Robert I. (Menlo Park CA) Adams Michael J. (San Jose CA) Prodanovich George L. (Campbell CA) Key Paul F. (San Martin CA) Rawlings Don O. (San Jose CA) Santhanam P. (Sunnyvale CA) Hunt Sus, Buffer storage apparatus for semiconductor wafer processing.
  3. Crabb Richard (Mesa AZ) Robinson McDonald (Paradise Valley AZ) Hawkins Mark R. (Mesa AZ) Goodwin Dennis L. (Tempe AZ) Ferro Armand P. (Scottsdale AZ) Ozias Albert E. (Aumsville OR) deBoer Wiebe B. (E, Chemical vapor deposition system.
  4. Ishii Katsumi (Fujino JPX) Asano Takanobu (Yokohama JPX) Abe Masaharu (Sagamihara JPX) Yamaga Kenichi (Sagamihara JPX) Sakata Kazunari (Sagamihara JPX) Tanahashi Takashi (Machida JPX) Moriya Syuji (Y, Clean air apparatus.
  5. Natsugari Hideaki,JPX ; Ishimaru Takenori,JPX ; Doi Takayuki,JPX ; Ikeura Yoshinori,JPX ; Kimura Chiharu,JPX ; Tarui Naoki,JPX, Cyclic compounds, their prudiction and use.
  6. Nogami Mamoru (Uji JPX), End station for an ion implantation apparatus.
  7. Devilbiss John J. (San Mateo CA) Glaze James A. (Danville CA) Lugosi Steve (Fremont CA) McNaughton Allen D. (Fremont CA) Ozaraki Robert G. (Livermore CA), Enhanced vertical thermal reactor system.
  8. Shidahara Hitoshi (Okayama JPX) Yamamoto Syozi (Ibara JPX), Equipment for heating and cooling substrates for coating photo resist thereto.
  9. Ohsawa Tetsu (Sagamihara JPX), Heat treating apparatus.
  10. Zajac John (San Jose CA) Mirkovich Ninko T. (Novato CA) Rathmann Thomas M. (Rohnert Park CA) Lachenbruch Roger B. (Petaluma CA), Modular article processing machine and method of article handling therein.
  11. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Wang David N. (Cupertino CA) Cheng David (San Jose CA) Toshima Masato (San Jose CA) Harari Isaac (Mountain View CA) Hoppe Peter D. (Sun, Multi-chamber integrated process system.
  12. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Wang David N. (Cupertino CA) Cheng David (San Jose CA) Toshima Masato (San Jose CA) Harari Isaac (Mountain View CA) Hoppe Peter D. (Sun, Multichamber integrated process system.
  13. Krueger Gordon P. (San Jose CA), Reducing particulates during semiconductor fabrication.
  14. Grunes Howard (Santa Cruz CA) Tepman Avi (Cupertino CA) Lowrance Robert (Los Gatos CA), Robot assembly.
  15. Bramhall ; Jr. Robert B. (Gloucester MA) Cloutier Richard M. (Salisbury MA) Laber Albert P. (Revere MA) Muka Richard S. (Topsfield MA), Sealing apparatus for a vacuum processing system.
  16. Tepman Avi (Cupertino CA) Grunes Howard (Santa Cruz CA) Somekh Sasson (Los Altos Hills CA) Maydan Dan (Los Altos Hills CA), Staged-vacuum wafer processing system and method.
  17. Lowrance Robert B. (Los Gatos CA), Two-axis magnetically coupled robot.
  18. Wagner Rudolf (Fontnas CHX) Martin Bader (Balzers LIX) Eberhard Moll (Schellenberg LIX) Zanardo Renzo (Balzers LIX) Van Agtmaal J. G. (Hilversum NLX), Vacuum apparatus.
  19. Galdos Aitor (Vaduz LIX) Wagner Rudolf (Weite CHX) Bruderer Markus (Widnau CHX), Vacuum apparatus for the surface treatment of workpieces.
  20. Toshima Masato (Campbell CA), Vacuum chamber slit valve.
  21. Fukasawa Yoshio (Kofu JPX) Hosoda Shozo (Yamanashi-ken JPX) Nakagome Tatsuya (Yamanashi-ken JPX) Tozawa Takashi (Yamanashi-ken JPX) Suzuki Koji (Yamanashi-ken JPX) Ishihara Yasumasa (Kofu JPX) Aoyagi, Vacuum process apparatus and vacuum processing method.
  22. Murata Masanao (Ise JPX) Yamashita Teppei (Ise JPX) Tanaka Tsuyoshi (Ise JPX) Hoshiko Takahide (Ise JPX) Karita Mitsuji (Ise JPX) Kawano Hitoshi (Ise JPX) Shinya Tutomu (Ise JPX), Wafer conveying system in a clean room.
  23. Chrisos John M. (Beverly MA) Fowler ; Jr. Bertram F. (Danvers MA) Muka Richard S. (Topsfield MA), Wafer handling apparatus.
  24. Flegal ; deceased Christopher (late of New City NY by Gisela H. Flegal ; legal representative), Wafer processing machine vacuum front end method and apparatus.
  25. Hertel Richard J. (Bradford MA) Delforge Adrian C. (Rockport MA) Mears Eric L. (Rockport MA) MacIntosh Edward D. (Gloucester MA) Jennings Robert E. (Nethuen MA) Bhargava Akhil (Reading MA), Wafer transfer system.
  26. Wiesler Mordechai (Lexington MA) Weiss Mitchell (Haverford PA), Wafer transfer system having rotational capability.
  27. Somekh Sasson (Los Altos Hills CA) Fairbairn Kevin (Saratoga CA) Kolstoe Gary M. (Fremont CA) White Gregory W. (San Carlos CA) Faraco ; Jr. W. George (Saratoga CA), Wafer tray and ceramic blade for semiconductor processing apparatus.

이 특허를 인용한 특허 (23)

  1. Lee,Jae Chull; Berkstresser,David, Curved slit valve door with flexible coupling.
  2. Lee, Jae-Chull; Kurita, Shinichi; White, John M.; Anwar, Suhail, Decoupled chamber body.
  3. Kurita, Shinichi; Blonigan, Wendell T., Double dual slot load lock chamber.
  4. Pietrantonio, Antonio F.; Chesna, Anthony; Elmali, Hakan; Gilchrist, Ulysses, Dual scara arm.
  5. Pietrantonio, Antonio F.; Chesna, Anthony; Elmoli, Hakan; Gilchrist, Ulysses, Dual scara arm.
  6. Kurita, Shinichi; Blonigan, Wendell T.; Hosokawa, Akihiro, Dual substrate loadlock process equipment.
  7. Kurita, Shinichi; Blonigan, Wendell T.; Hosokawa, Akihiro, Dual substrate loadlock process equipment.
  8. Kurita, Shinichi; Blonigan, Wendell T.; Tanase, Yoshiaki, Large area substrate transferring method for aligning with horizontal actuation of lever arm.
  9. Kurita,Shinichi; Blonigan,Wendell T.; Tanase,Yoshiaki, Load lock chamber for large area substrate processing system.
  10. Kurita,Shinichi; Blonigan,Wendell T., Load lock chamber having two dual slot regions.
  11. Lee, Jae-Chull; Anwar, Suhail; Kurita, Shinichi, Load lock chamber with decoupled slit valve door seal compartment.
  12. Van Den Berg,Jannes Remco, Method and apparatus for loading a batch of wafers into a wafer boat.
  13. De Ridder, Christianus Gerardus Maria, Method and system for loading substrate supports into a substrate holder.
  14. De Ridder,Christianus Gerardus Maria, Method and system for loading substrate supports into a substrate holder.
  15. Kurita,Shinichi; Blonigan,Wendell T., Method for transferring substrates in a load lock chamber.
  16. Kurita, Shinichi; Anwar, Suhail; Lee, Jae-Chull, Multiple slot load lock chamber and method of operation.
  17. Borden, Peter G., Stacked load-lock apparatus and method for high throughput solar cell manufacturing.
  18. Enokida, Suguru; Nakaharada, Masahiro; Miyata, Akira; Kiyama, Hidekazu; Iida, Naruaki, Substrate processing apparatus, substrate processing method and storage medium.
  19. Aggarwal, Ravinder; Kusbel, Jim; Alexander, Jim, System for the improved handling of wafers within a process tool.
  20. Kevin K. Chan ; Christopher P. D'Emic ; Raymond M. Sicina ; Paul M. Kozlowski ; Margaret Manny ; Sandip Tiwari, UHV horizontal hot wall cluster CVD/growth design.
  21. Kim, Sam Hyungsam; Lee, Jae-Chull; Sterling, William N.; Brown, Paul, Valve door with ball coupling.
  22. Sieradzki,Manny; White,Nicholas R., Wafer handling apparatus and method.
  23. Simeon Richard, XDSL modem having time domain filter for ISI mitigation.
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