초록 ▼

An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance master, slave, master/slave, bus controller, and bus monitor type modules. Each circuit module is an on-ch

An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance master, slave, master/slave, bus controller, and bus monitor type modules. Each circuit module is an on-chip function block including a bus interface and communicates by a predefined set of bus signals; at least one module is an FPGA (field programmable gate array). Each module acts as a bus master when it initiates data read or write operations, or may be addressed during a bus read/write operation and thereby acts as a bus slave. This bus and module structure allows implementation of a system on a single chip.

대표청구항 ▼

[ I claim:] [1.] An integrated circuit device comprising:a bus comprising a plurality of bus lines;a plurality of modules, at least one of the modules comprising an FPGA, the FPGA comprising:a plurality of configurable logic blocks; anda plurality of interconnect lines for interconnecting the logic

[ I claim:] [1.] An integrated circuit device comprising:a bus comprising a plurality of bus lines;a plurality of modules, at least one of the modules comprising an FPGA, the FPGA comprising:a plurality of configurable logic blocks; anda plurality of interconnect lines for interconnecting the logic blocks;for each module, an associated interface structure for driving signals from the module onto the bus lines and for applying signals on the bus lines to the modulemeans for configuring the bus and the FPGA; anda bus arbiter coupled to the bus for selecting which of the interface structures can drive signals onto the bus.