초록 ▼

A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which

A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.epsilon. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

대표청구항 ▼

[ What is claimed is:] [1.] An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-.epsilon. material are utilized for fabricating the interconnect structure, and the interconnect conductors are fully encapsul

[ What is claimed is:] [1.] An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-.epsilon. material are utilized for fabricating the interconnect structure, and the interconnect conductors are fully encapsulated, said integrated circuit comprising:an underlying dielectric layer,a conductive region comprising deposited copper formed in said underlying dielectric layer, said conductive region having an upper surface,a conductive barrier/encapsulation layer selectively formed over said conductive region upper surface,a first inter-level dielectric ("ILD") layer formed over said conductive barrier/encapsulation layer and said first dielectric layer, said first ILD layer comprising low-.epsilon. material having a dielectric constant of less than 4,a first capping dielectric layer formed over said first ILD layer,a second ILD layer formed over said first capping dielectric layer and comprising low-.epsilon. material having a dielectric constant of less than 4,a second capping dielectric layer formed over said second ILD layer,a via opening extending through said first ILD layer and said first capping layer to the surface of said conductive barrier/encapsulation layer,a trench opening extending through said second ILD layer and said second capping layer, and connecting with said via opening,a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings, said conductive adhesion/barrier layer connecting to said conductive barrier/encapsulation layer and extending to the top of said second capping dielectric layer;continuous copper material filling the volume defined by said conductive adhesion/barrier layer and having a top surface; anda conductive barrier/encapsulation layer selectively formed over and capping said top surface of said continuous copper material, said conductive barrier/encapsulation layer joining with said conductive adhesion/barrier layer thus to fully encapsulate said continuous copper material.