초록 ▼

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

대표청구항 ▼

[ What is claimed is:] [10.] A programmable memory circuit comprising an array of bit/word line addressable memory cells including:a first memory cell addressable per a first word line for enabling primary data access thereto;a second memory cell addressable per a second word line, for enabling prim

[ What is claimed is:] [10.] A programmable memory circuit comprising an array of bit/word line addressable memory cells including:a first memory cell addressable per a first word line for enabling primary data access thereto;a second memory cell addressable per a second word line, for enabling primary data access thereto;a transfer cell disposed intermediate said first memory cell and said second memory cell for providing intermediate data storage;a first selective coupler enabled per a first clock for selectively coupling said transfer cell and said first memory cell, enabling data propagation therebetween; anda second selective coupler enabled per a second clock for selectively coupling said transfer cell and said second memory cell, enabling data propagation therebetween;whereby said first and second clocks are operated sequentially for transferring data from one of said first and second memory cells to the other.