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Method and apparatus for processing data in a neural network 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06E-001/00
  • G06E-003/00
출원번호 US-0839818 (1997-04-18)
발명자 / 주소
  • Meng Wan-Yu,TWX
  • Chang Cheng-Kai,TWX
  • Chang Hwai-Tsu,TWX
  • Hsu Fang-Ru,TWX
  • Lee Ming-Rong,TWX
출원인 / 주소
  • Industrial Technology Research Institute, TWX
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보 피인용 횟수 : 51  인용 특허 : 8

초록 ▼

A digital artificial neural network (ANN) reduces memory requirements by storing sample transfer function representing output values for multiple nodes. Each nodes receives an input value representing the information to be processed by the network. Additionally, the node determines threshold values

대표청구항 ▼

[ What is claimed is:] [1.] An apparatus for processing data in a neural network having a stored sample transfer function, comprising:a receiver configured to receive at least one input value representing information to be processed by the network;a threshold processor configured to determine thresh

이 특허에 인용된 특허 (8)

  1. Davidian David (Cambridge MA), Feed-forward neural network.
    상세보기
  2. Cooper Leon N. (Providence RI) Elbaum Charles (Providence RI), Information processing system.
    상세보기
  3. White James A. (1757 20th Ave. New Brighton MN 55112), Mask controled neural networks.
    상세보기
  4. Thrift Philip (9823 Summerwood Cir. Apt. 2004 Dallas TX 75243), Method and apparatus for adaptive learning in neural networks.
    상세보기
  5. Skapura David M. (Friendswood) McIntire Gary J. (Friendswood TX), Method of implementing a neural network on a digital computer.
    상세보기
  6. Watanabe Takao (Inagi JPX) Kimura Katsutaka (Akishima JPX) Itoh Kiyoo (Higashikurume JPX) Kawajiri Yoshiki (Hachioji JPX), Neural network processing system using semiconductor memories.
    상세보기
  7. Shimokawa Yoshiyuki (Tokyo JPX), Neuro-chip and neurocomputer having the chip.
    상세보기
  8. Furuta Toshiyuki (Yokohama JPX) Horiguchi Hiroyuki (Yokohama JPX) Eguchi Hirotoshi (Yokohama JPX) Ebi Yutaka (Yokohama JPX) Furukawa Tatsuya (Yokohama JPX) Watanabe Yoshio (Kawasaki JPX) Tsukagoshi T, Neuron unit, neural network and signal processing method.
    상세보기

이 특허를 인용한 특허 (51)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
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  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
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  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
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  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
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  16. Hammond, Jeremy, Automated calibration method and system for a diagnostic analyzer.
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  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
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  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
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  19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
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  20. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
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  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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  22. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  24. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
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  25. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  26. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  29. Luo, Fa-Long; Uvacek, Bohumir, IC for universal computing with near zero programming complexity.
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  30. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  31. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  32. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  33. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
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  34. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
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  35. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  36. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  39. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  40. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  41. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  43. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
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  44. Hunzinger, Jason Frank; Chan, Victor Hokkiu, Methods and apparatus for neural component memory transfer of a referenced pattern by including neurons to output a pattern substantially the same as the referenced pattern.
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  45. Hunzinger, Jason Frank; Chan, Victor Hokkiu, Methods and apparatus for neural pattern sequence completion and neural pattern hierarchical replay by invoking replay of a referenced neural pattern.
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  46. Hunzinger, Jason Frank; Chan, Victor Hokkiu, Methods and apparatus for unsupervised neural component replay by referencing a pattern in neuron outputs.
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  47. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
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  48. Master,Paul L.; Watson,John, Storage and delivery of device features.
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  49. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
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  50. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
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  51. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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