초록 ▼

A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermin

A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermined command transmitted over the bus causes the scan test ports to be coupled to the bus and the input/output ports to be decoupled from the bus. Test data may then be transmitted to and from the logic circuits via the bus. When testing is complete, a second predetermined command transmitted over the bus causes the scan test ports to be decoupled from the bus and the input/output ports to be coupled to the bus.

대표청구항 ▼

[ I claim:] [1.] A scan testable circuit arrangement, comprising:a bus;a plurality of logic circuits, each logic circuit having a plurality of scan test ports and a plurality input/output ports;a first plurality of switches, each having a first terminal coupled to a predetermined signal line of the

[ I claim:] [1.] A scan testable circuit arrangement, comprising:a bus;a plurality of logic circuits, each logic circuit having a plurality of scan test ports and a plurality input/output ports;a first plurality of switches, each having a first terminal coupled to a predetermined signal line of the bus and a second terminal coupled to a respective one of the scan test ports of the logic circuits;a second plurality of switches, each having a first terminal coupled to a predetermined signal line of the bus and a second terminal coupled to a respective one of input/output ports of the logic circuits;a plurality of command decoders, coupled to the bus to receive bus commands and coupled to the gates of the first and second plurality of switches, configured and arranged to couple the scan test ports to the bus for a first operational mode responsive to a first set of the bus commands, and couple the input/output ports to the bus for a second operational mode responsive to a second set of commands anda buffer circuit arranged to couple the bus to a local bus; anda bypass circuit coupled to the bus and arranged to couple the bus to the local bus and bypass the buffer circuit during the first operational mode.