$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

System, method, and program product for loop instruction scheduling hardware lookahead 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/44
출원번호 US-0882724 (1997-06-23)
발명자 / 주소
  • Simons Barbara Bluestein
  • Sarkar Vivek
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Johnson
인용정보 피인용 횟수 : 32  인용 특허 : 22

초록

Improved scheduling of instructions within a loop for execution by a computer system having hardware lookahead is provided. A dependence graph is constructed which contains all the nodes of a dependence graph corresponding to the loop, but which only contains loop-independent dependence edges. A sta

대표청구항

[ We claim:] [1.] A method of scheduling a plurality of instructions of a loop for execution by a processor having a lookahead buffer, said method comprising the steps of:constructing a dependence graph comprising nodes and edges corresponding to the loop;constructing a loop-independent dependence g

이 특허에 인용된 특허 (22)

  1. Kitta Mayumi (Yamanashi JPX), Arrangement for predicting a branch target address in the second iteration of a short loop.
  2. Potash Hanan (La Jolla CA), Branch predicting computer.
  3. Brown ; III John F. (Northboro MA) Persels Shawn (Northboro MA) Meyer Jeanne (Watertown MA), Branch prediction unit for high-performance processor.
  4. Jain Suneel (San Jose CA) Chow Frederick (Cupertino CA) Chan Sun (Fremont CA) Lew Sin S. (San Jose CA), Circular scheduling method and apparatus for executing computer programs by moving independent instructions out of a loo.
  5. Moore ; Jr. William T. (Elk Mound WI), Computer look-ahead instruction issue control.
  6. Morisada Tsuyoshi (Tokyo JPX), Device for effectively controlling a branch history table for an instruction prefetching system even if predictions are.
  7. Okamoto Kosei (Kunitachi JPX), Instruction pipeline microprocessor.
  8. Oklobdzija Vojin G. (Putnam County NY) Ling Daniel T. (Westchester County NY), Instruction prefetch buffer control.
  9. Shibuya Toshiteru (Tokyo JPX), Instruction prefetching device having a history table for memorizing page last real instruction addresses and page-over.
  10. Hanatani Syuichi (Tokyo JPX) Akagi Masanobu (Tokyo JPX) Nigo Kouemon (Tokyo JPX) Sugaya Ritsuo (Tokyo JPX) Shibuya Toshiteru (Tokyo JPX), Instruction prefetching device with prediction of a branch destination address.
  11. Tarsy Gregory (Scotts Valley CA) Woodard Michael J. (Fremont CA), Method and apparatus for cost-based heuristic instruction scheduling.
  12. Kodama Takashi (Kanagawa JPX), Method and apparatus for parallel loads equalizing utilizing instruction sorting by columns based on predicted instructi.
  13. Langendorf Brian K. (Worcester MA), Method and apparatus for qualifying branch cache entries.
  14. Rasbold James C. (Livermore CA) Van Dyke Don A. (Pleasanton CA), Method for inserting a path instruction during compliation of computer programs for processors having multiple functiona.
  15. Rasbold James C. (Livermore CA) Van Dyke Don A. (Pleasanton CA), Method for optimizing instruction scheduling for a processor having multiple functional resources.
  16. Witt David B. ; Johnson William M., Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register.
  17. Gupta Rajiv (Ossining NY), Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data depe.
  18. Keckler Stephen W. (Cambridge MA) Dally William J. (Framingham MA), Multiprocessor coupling system with integrated compile and run time scheduling for parallelism.
  19. Duxbury Colin M. (Stockport GB3) Eaton John R. (Lancashire GB3) Rose Philip V. (Manchester GB3), Pipelined processor with look-ahead mode of operation.
  20. Hodges Steven E. (Stockport GB3), Pipelined system includes correction mechanism operated on history information identifying conditional jump instructions.
  21. Uht Augustus K. (44 Torrey Rd. Cumberland RI 02864), System for extracting low level concurrency from serial instruction streams.
  22. Simons Barbara Bluestein ; Sarkar Vivek, System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by th.

이 특허를 인용한 특허 (32)

  1. Burger, Douglas C.; Smith, Aaron; Gray, Jan, Age-based management of instruction blocks in a processor instruction window.
  2. Matichuk,Bruce, Application integration system and method using intelligent agents for integrating information access over extended networks.
  3. James M. Crawford, Jr. ; Mukesh Dalal ; Joachim Paul Walser DE, Computer implemented scheduling system and process using abstract local search technique.
  4. Gonion, Jeffry E.; Diefendorff, Keith E., Conditional data-dependency resolution in vector processors.
  5. Gonion, Jeffry E., Conditional stop instruction with accurate dependency detection.
  6. Rumph,Darryl Jonathan, Configurable hardware scheduler calendar search algorithm.
  7. Bics?k,Attila; Kiss,?kos; Ferenc,Rudolf; Gyim?thy,Tibor, Constructing control flows graphs of binary executable programs at post-link time.
  8. Nystad, Jorn, Data processing systems.
  9. Gray, Jan; Burger, Doug; Smith, Aaron, Explicit instruction scheduler state information for a processor.
  10. Martin, Allan Russell, Extension of swing modulo scheduling to evenly distribute uniform strongly connected components.
  11. Martin,Allan Russell, Extension of swing modulo scheduling to evenly distribute uniform strongly connected components.
  12. Robison, Arch D., Fast tree-based generation of a dependence graph.
  13. Gonion, Jeffry E.; Diefendorff, Keith E., Generating stop indicators based on conditional data dependency in vector processors.
  14. Waki, Hiroyuki; Inoue, Shinji; Hayama, Satoru; Fujita, Mitsuko; Ishikawa, Akira, High speed virtual machine and compiler.
  15. Burger, Douglas C.; Smith, Aaron L., Instruction block address register.
  16. Christopher M. McKinsey ; Jayashankar Bharadwaj, Interactive instruction scheduling and block ordering.
  17. Stotzer Eric ; Scales Richard H., Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers.
  18. Burger, Doug, Locking operand values for groups of instructions executed atomically.
  19. Burger, Douglas C.; Smith, Aaron; Gray, Jan, Mapping instruction blocks based on block size.
  20. Guo, Xiaofeng; Dai, Jinquan; Li, Long, Method and apparatus for merging critical sections.
  21. Hamadi,Youssef; Chong,Yek Loong; Shapiro,Marc, Ordering decision nodes in distributed decision making.
  22. Van De Waerdt, Jan-Willem; Roos, Steven, Pipelined processor and compiler/scheduler for variable number branch delay slots.
  23. Burger, Doug; Smith, Aaron, Processing an encoding format field to interpret header information regarding a group of instructions.
  24. Heishi, Taketo; Michimoto, Shohei; Kawabata, Teruo, Program converting apparatus and program conversion method.
  25. Mahlke, Scott A.; Abraham, Santosh G.; Kathail, Vinod K., Retargetable computer design system.
  26. Burger, Douglas Christopher; Smith, Aaron, Reuse of decoded instructions.
  27. Rumph,Darryl J., Scalable hardware scheduler time based calendar search algorithm.
  28. Guo, Xiaofeng; Dai, Jinquan; Li, Long, Scheduling multithreaded programming instructions based on dependency graph.
  29. Rong, Hongbo; Park, Hyunchul; Wu, Youfeng, Software pipelining at runtime.
  30. Hindi, Haitham Ali; Ruml, Wheeler, System and method for manufacturing system design and shop scheduling using network flow modeling.
  31. Lee,Lea Hwang; Moyer,William C., System for expanded instruction encoding and method thereof.
  32. Tameshige, Takashi; Kudou, Yutaka; Morimura, Tomohiro; Teramura, Takeshi; Iizuka, Daisuke; Ozaki, Nobuaki, System management method, management computer, and non-transitory computer-readable storage medium.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로