초록 ▼

A first-in first-out (FIFO) memory interface is provided by coupling an input register and an output register to a conventional static random access memory (SRAM). The registers and SRAM are coupled to control logic that controls the timing of shift-in (write) and shift-out (read) operations. Upon r

A first-in first-out (FIFO) memory interface is provided by coupling an input register and an output register to a conventional static random access memory (SRAM). The registers and SRAM are coupled to control logic that controls the timing of shift-in (write) and shift-out (read) operations. Upon receipt of a write request signal, input data is received from the requesting device and buffered within the input register. The buffered data is then stored in the SRAM during a write operation. Upon receipt of a read request signal, the data previously buffered in the output register is provided to the requesting device and during an associated read operation the next stored data in the SRAM is retrieved and buffered within the output register. The control logic is programmable and is therefore capable of supporting different SRAM configurations. The control logic can also be implemented in a conventional programmable logic device.

대표청구항 ▼

[ What is claimed is:] [1.] A first-in first-out (FIFO) apparatus for use with an external input device and an external output device, the apparatus comprising:memory configured to store data during a write operation and output the stored data during a read operation;an input register coupled to the

[ What is claimed is:] [1.] A first-in first-out (FIFO) apparatus for use with an external input device and an external output device, the apparatus comprising:memory configured to store data during a write operation and output the stored data during a read operation;an input register coupled to the memory and configured to buffer input data from an external input device and output at least a portion of the buffered input data to the memory during the write operation;an output register coupled to the memory and configured to buffer the stored data output by the memory during the read operation and output at least a portion of the buffered stored data to an external output device;logic at least externally coupled to the memory, the input register and the output register, and configured to control the write operation in response to a write request signal from the external input device, and the read operation in response to a read request signal from the external output device;a means for verifying that the memory is not full and that a previous write operation is not being conducted prior to buffering the input data in the input register; anda means for verifying that the memory is not empty and that a previous read operation is not being conducted prior to accessing the stored data within the memory.